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14 件の該当がありました. : このページのURL : HTML


論文誌
[1] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing," IEEE Transactions on Nuclear Science, volume 70, number 8, 1652 -- 1657, August 2023. [pdf]
[2] T. Kato, M. Tampo, S. Takeshita, H. Tanaka, H. Matsuyama, M. Hashimoto, and Y. Miyake, "Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha Particles," IEEE Transactions on Nuclear Science, volume 68, number 7, pages 1436-1444, July 2021. [pdf]
[3] T. Kato, M. Hashimoto, and H. Matsuyama, "Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs with Comparison to 20-nm Planar SRAMs," IEEE Transactions on Nuclear Science, volume 67, number 7, 1485 -- 1493, July 2020. [pdf]
[4] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Exploring Well-Configurations for Minimizing Single Event Latchup," IEEE Transactions on Nuclear Science, volume 61, number 6, pages 3282--3289, December 2014. [211.pdf]
[5] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013. [197.pdf]
[6] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4232--4237, December 2013. [198.pdf]
国際会議
[1] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.
[2] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [215.pdf]
[3] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]
[4] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Optimizing Well-Configuration for Minimizing Single Event Latchup," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[5] T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, "Preventing Single Event Latchup with Deep P-Well on P-Substrate," Proceedings of International Reliability Physics Symposium (IRPS), June 2014. [203.pdf]
[6] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[7] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[8] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.