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21 件の該当がありました． : このページのURL : HTML

論文誌

[1] Y. Gomi, A. Sato, W. Madany, K. Okada, S. Adachi, M. Itoh, and M.Hashimoto, "A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement," IEEE Solid-State Circuits Letters, volume 8, pages 245-248, September 2025. [pdf]

[2] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, volume 69, pages 161--179, November 2019. [pdf]

[3] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 867--877, July 2019. [pdf]

[4] W. Liao and M. Hashimoto, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, volume E102-C, number 4, pages 296--302, April 2019. [pdf]

[5] Y. Masuda, T. Onoye, and M. Hashimoto, "Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E100-A, number 7, pages 1452--1463, July 2017. [pdf]

[6] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), volume 10, number 5, April 2013. [184.pdf]

国際会議

[1] T. Tanaka, T. Uezono, K. Suenaga, and M. Hashimoto, "Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 966 - 973, January 2025. [pdf]

[2] M. Hashimoto, R. Yasuda, K. Takami, Y. Gomi, and K. Takeuchi, "ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 379 - 384, January 2025. [pdf]

[3] Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, "How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --," Proceedings of Design Automation Conference (DAC), June 2024. [pdf]

[4] M. Niikura, R. Mizuno, S. Manabe, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, A. Hillier, N. Kawamura, Y. Kawashima, S. Kawase, T. Kawata, K. Kitafuji, F. Minato, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, M. Tampo, D. Tomono, I. Umegaki, Y. Yamaguchi, and Y. Watanabe, "Nuclear Physics for Muon-Induced Soft Error," Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis, August 2023.

[5] K. Ito, H. Itsuji, T. Uezono, T. Toba, M. Itoh, and M. Hashimoto, "Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022. [pdf]

[6] M. Hashimoto, Y. Zhang, and K. Ito, "Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards," Proceedings of International Conference on Solid State Devices and Materials (SSDM), September 2022.

[7] M. Hashimoto and W. Liao, "Soft Error and Its Countermeasures in Terrestrial Environment," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020. [pdf]

[8] M. Hashimoto, W. Liao, S. Manabe, and Y. Watanabe, "Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2018. [pdf]

[9] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [pdf]

[10] M. Hashimoto, W. Liao, and S. Hirokawa, "Soft Error Rate Estimation with TCAD and Machine Learning (Invited)," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2017. [pdf]

[11] W. Liao, S. Hirokawa, R. Harada, and M. Hashimoto, "Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V --," Proceedings of International NEWCAS Conference, pages 33-37, June 2017. [pdf]

[12] S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, and M. Hashimoto, "Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2016. [pdf]

[13] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]

[14] M. Hashimoto, "Soft Error Immunity of Subthreshold SRAM (Invited)," Proceedings of IEEE International Conference on ASIC, pages 91--94, October 2013. [192.pdf]

[15] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient VLSI Architecture for Signal Processing," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009. [142.pdf]