Table of works
Frequent tags in this search: error:21 soft:14 rate:6 sram:6 bulk:3 circuit:3 design:3 detection:3 ff:3 invited:3 neutron-induced:3 timing:3 adaptively:2 characterizing:2 chip-level:2 circuits:2 combinational:2 errors:2 estimation:2 gpu:2 learning:2 machine:2 measurement:2 methodology:2 mttf-aware:2 neutron:2 rates:2 0.5:1 1.0v:1 125:1
21 publications are found. : URL for this page. : HTML
| Author (author) | Title (title) | Journal/Conference | Volume / Number | Pages (pages) | Published date | Impact factor / Acceptance | File | |
|---|---|---|---|---|---|---|---|---|
| Academic Journal |
|
A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement |
IEEE Solid-State Circuits Letters | 8 |
245-248 |
September 2025 |
pdf | |
| Academic Journal |
M. Hashimoto, K. Kobayashi, , S. Abe, Y. Watanabe |
Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited) |
Integration, the VLSI Journal | 69 |
161--179 |
November 2019 |
pdf | |
| Academic Journal |
Y. Masuda, M. Hashimoto |
MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | 102-A(7) |
867--877 |
July 2019 |
pdf | |
| Academic Journal |
W. Liao, M. Hashimoto |
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate |
IEICE Trans. on Electronics | E102-C(4) |
296--302 |
April 2019 |
pdf | |
| Academic Journal |
Y. Masuda, T. Onoye, M. Hashimoto |
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | E100-A(7) |
1452--1463 |
July 2017 |
pdf | |
| Academic Journal |
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye |
PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices |
IEICE Electronics Express (ELEX) | 10(5) |
April 2013 |
184.pdf | ||
| International Conference |
, , , M. Hashimoto |
Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | 966 - 973 |
January 2025 |
pdf | ||
| International Conference |
M. Hashimoto |
ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | 379 - 384 |
January 2025 |
pdf | ||
| International Conference |
, , , W. Liao, , , M. Hashimoto |
How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC -- |
Proceedings of Design Automation Conference (DAC) | June 2024 |
pdf | |||
| International Conference |
, , S. Manabe, , , S. Abe, , M. Hashimoto, , , , , , , , , , , , , , M. Tampo, , , , Y. Watanabe |
Nuclear Physics for Muon-Induced Soft Error |
Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis | August 2023 |
||||
| International Conference |
, , , , , M. Hashimoto |
Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment |
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) | October 2022 |
pdf | |||
| International Conference |
M. Hashimoto, Y. Zhang |
Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards |
Proceedings of International Conference on Solid State Devices and Materials (SSDM) | September 2022 |
||||
| International Conference |
M. Hashimoto, W. Liao |
Soft Error and Its Countermeasures in Terrestrial Environment |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | January 2020 |
pdf | |||
| International Conference |
M. Hashimoto, W. Liao, S. Manabe, Y. Watanabe |
Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams (Invited) |
Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) | October 2018 |
pdf | |||
| International Conference |
Y. Masuda, M. Hashimoto |
MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | January 2018 |
pdf | |||
| International Conference |
M. Hashimoto, W. Liao, S. Hirokawa |
Soft Error Rate Estimation with TCAD and Machine Learning (Invited) |
Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) | September 2017 |
pdf | |||
| International Conference |
W. Liao, S. Hirokawa, R. Harada, M. Hashimoto |
Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V -- |
Proceedings of International NEWCAS Conference | 33-37 |
June 2017 |
pdf | ||
| International Conference |
S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, M. Hashimoto |
Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning |
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) | September 2016 |
pdf | |||
| International Conference |
T. Uemura, S. Okano, T. Kato, H. Matsuyama, M. Hashimoto |
Soft Error Immune Latch Design for 20 nm Bulk CMOS |
Proceedings of International Reliability Physics Symposium (IRPS) | April 2015 |
217.pdf | |||
| International Conference |
M. Hashimoto |
Soft Error Immunity of Subthreshold SRAM (Invited) |
Proceedings of IEEE International Conference on ASIC | 91--94 |
October 2013 |
192.pdf | ||
| International Conference |
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye |
Soft Error Resilient VLSI Architecture for Signal Processing |
Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) | 183--186 |
December 2009 |
142.pdf |