この検索内の頻出タグ: design^:21 methodology^:6 soc^:5 voltage^:5 scaling^:4 bit-width^:3 cmos^:3 critical^:3 error^:3 isolation^:3 mttf-aware^:3 over-scalable^:3 path^:3 activation-aware^:2 adaptively^:2 analysis^:2 assignment^:2 circuit^:2 energy^:2 extraction^:2 flattening^:2 gradient^:2 inductance^:2 interconnect^:2 invited^:2 minimization^:2 mode-wise^:2 modeling^:2 on-chip^:2 power^:2

21 件の該当がありました． : このページのURL : HTML

論文誌

[1] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]

[2] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 867--877, July 2019. [pdf]

[3] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]

[4] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]

国際会議

[1] M. Hashimoto and J. Chen, "Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2021. [pdf]

[2] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]

[3] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]

[4] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020.

[5] S. Sombatsiri, J. Yu, M. Hashimoto, and Y. Takeuchi, "A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2019.

[6] M. Hashimoto and Y. Masuda, "MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018. [pdf]

[7] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [pdf]

[8] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [pdf]

[9] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]

[10] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]

[11] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix LCD," In Proceedings of European Conference on Circuit Theory and Design, number 3e-212, August 2005. [54.pdf]

[12] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]

[13] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), D9-D10, January 2005. [35.pdf]

[14] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of CMOS Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pages 434-435, August 2004. [55.pdf]

[15] H. Onodera, M. Hashimoto, and T. Hashimoto, "ASIC Design Methodology with On-Demand Library Generation," In Proceedings of Symposium on VLSI Circuits, pages 57-60, June 2001. [59.pdf]

研究会・全国大会等

[1] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.

著書

[1] T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, and J. Yao, "Time-Dependent Degradation in Device Characteristics and Countermeasures by Design," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.