Table of works
Frequent tags in this search: design:23 methodology:6 soc:5 voltage:5 cmos:4 scaling:4 analysis:3 bit-width:3 critical:3 error:3 isolation:3 mttf-aware:3 over-scalable:3 path:3 activation-aware:2 adaptively:2 assignment:2 circuit:2 energy:2 extraction:2 flattening:2 gradient:2 inductance:2 interconnect:2 invited:2 low-power:2 matrix:2 minimization:2 mode-wise:2 modeling:2
23 publications are found. : URL for this page. : HTML
| Author (author) | Title (title) | Journal/Conference | Volume / Number | Pages (pages) | Published date | Impact factor / Acceptance | File | |
|---|---|---|---|---|---|---|---|---|
| Academic Journal |
, , , , , , M. Hashimoto |
Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS |
IEEE Transactions on Circuits and Systems II | (accepted, to appear) |
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| Academic Journal |
, M. Hashimoto |
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | 105-A(3) |
509--517 |
March 2022 |
pdf | |
| Academic Journal |
Y. Masuda, M. Hashimoto |
MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | 102-A(7) |
867--877 |
July 2019 |
pdf | |
| Academic Journal |
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto |
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | E89-A(12) |
3560-3568 |
December 2006 |
3.pdf | |
| Academic Journal |
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto |
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences | E88-A(12) |
3382-3389 |
December 2005 |
9.pdf | |
| International Conference |
and |
Gundam: a Generalized Unified Design and Analysis Model for Matrix Multiplication on Edge |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | (accepted, to appear) |
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| International Conference |
M. Hashimoto, J. Chen |
Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution (Invited) |
Proceedings of China Semiconductor Technology International Conference (CSTIC) | March 2021 |
pdf | |||
| International Conference |
Y. Masuda, , , , , M. Hashimoto |
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design |
Proceedings of Design, Automation and Test in Europe Conference (DATE) | February 2021 |
pdf | |||
| International Conference |
, Y. Masuda, , , J. Chen, M. Hashimoto |
Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | 284 -- 290 |
January 2021 |
pdf | ||
| International Conference |
Y. Masuda, , , , , M. Hashimoto |
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling |
International Workshop on Logic and Synthesis (IWLS) | July 2020 |
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| International Conference |
, J. Yu, M. Hashimoto |
A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform |
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI) | October 2019 |
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| International Conference |
M. Hashimoto, Y. Masuda |
MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited) |
Proceedings of China Semiconductor Technology International Conference (CSTIC) | March 2018 |
pdf | |||
| International Conference |
Y. Masuda, M. Hashimoto |
MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | January 2018 |
pdf | |||
| International Conference |
S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, M. Hashimoto |
Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes |
Proceedings of International Symposium on Antennas and Propagation (ISAP) | October 2016 |
pdf | |||
| International Conference |
T. Uemura, S. Okano, T. Kato, H. Matsuyama, M. Hashimoto |
Soft Error Immune Latch Design for 20 nm Bulk CMOS |
Proceedings of International Reliability Physics Symposium (IRPS) | April 2015 |
217.pdf | |||
| International Conference |
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto |
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design |
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI) | 227-230 |
May 2006 |
65.pdf | ||
| International Conference |
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa |
A Design Scheme for Sampling Switch in Active Matrix LCD |
Proceedings of European Conference on Circuit Theory and Design | (3e-212) |
August 2005 |
54.pdf | ||
| International Conference |
T. Sato, N. Ono, J. Ichimiya, K. Hachiya, M. Hashimoto |
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | 1074-1077 |
January 2005 |
34.pdf | ||
| International Conference |
A. Shinmyo, M. Hashimoto, H. Onodera |
Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process |
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) | D9-D10 |
January 2005 |
35.pdf | ||
| International Conference |
A. Shinmyo, M. Hashimoto, H. Onodera |
Design and Optimization of CMOS Current Mode Logic Dividers |
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 434-435 |
August 2004 |
55.pdf | ||
| International Conference |
H. Onodera, M. Hashimoto, T. Hashimoto |
ASIC Design Methodology with On-Demand Library Generation |
Proceedings of Symposium on VLSI Circuits | 57-60 |
June 2001 |
59.pdf | ||
| Workshop |
, Y. Masuda, , , J. Chen, M. Hashimoto |
Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization |
電子情報通信学会 VLSI設計技術研究会 | March 2021 |
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| Book |
T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao |
Time-Dependent Degradation in Device Characteristics and Countermeasures by Design |
Book chapter, VLSI Design and Test for Systems Dependability, Springer | August 2018 |