Detail of a work
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T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E89-A(12), pp. 3560-3568, December 2006. | |
ID | 5 |
分類 | 論文誌 |
タグ | design extraction inductance interconnect modeling resistance si-substrate soc substrate-aware toward |
表題 (title) |
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design |
表題 (英文) |
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著者名 (author) |
T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto |
英文著者名 (author) |
T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto |
キー (key) |
T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto |
定期刊行物名 (journal) |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences |
定期刊行物名 (英文) |
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巻数 (volume) |
E89-A |
号数 (number) |
12 |
ページ範囲 (pages) |
3560-3568 |
刊行月 (month) |
12 |
出版年 (year) |
2006 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | 3.pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id5, title = {Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in {SoC} Design}, author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto}, journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences}, volume = {E89-A}, number = {12}, pages = {3560-3568}, month = {12}, year = {2006}, } |