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論文誌

[1] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]

国際会議

[1] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]

[2] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction," In Proceedings of International Workshop on Compact Modeling (IWCM), pages 51-56, January 2006.