: T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design, May 2006.
Detail of a work
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| T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227-230, May 2006. | |
| ID | 35 |
| 分類 | 国際会議 |
| タグ | design extraction inductance interconnect modeling resistance si-substrate soc substrate-aware toward |
| 表題 (title) |
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design |
| 表題 (英文) |
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| 著者名 (author) |
T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto |
| 英文著者名 (author) |
T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto |
| 編者名 (editor) |
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| 編者名 (英文) |
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| キー (key) |
T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto |
| 書籍・会議録表題 (booktitle) |
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI) |
| 書籍・会議録表題(英文) |
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| 巻数 (volume) |
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| 号数 (number) |
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| ページ範囲 (pages) |
227-230 |
| 組織名 (organization) |
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| 出版元 (publisher) |
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| 出版元 (英文) |
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| 出版社住所 (address) |
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| 刊行月 (month) |
5 |
| 出版年 (year) |
2006 |
| 採択率 (acceptance) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 65.pdf (application/pdf) [一般閲覧可] |
| BiBTeXエントリ |
@inproceedings{id35,
title = {Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in {SoC} Design},
author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto},
booktitle = {Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)},
pages = {227-230},
month = {5},
year = {2006},
}
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