この検索内の頻出タグ: extraction^:10 interconnect^:8 frequency^:4 representative^:3 rl^:3 c^:2 design^:2 f^:2 inductance^:2 l^:2 modeling^:2 r^:2 resistance^:2 si-substrate^:2 soc^:2 substrate-aware^:2 toward^:2 capacitance^:1 characteristics^:1 circuits^:1 determination^:1 errors^:1 estimation^:1 impact^:1 intrinsic^:1 lcd^:1 loop^:1 noise^:1 parasitic^:1 path^:1

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論文誌

[1] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3585-3593, December 2006. [2.pdf]

[2] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]

[3] T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M. Hashimoto, "Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3666-3670, December 2006. [5.pdf]

[4] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2942-2951, December 2003. [14.pdf]

国際会議

[1] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]

[2] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006. [30.pdf]

[3] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pages 160-163, April 2005. [29.pdf]

[4] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop RL Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005. [33.pdf]

[5] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 691-696, January 2004. [37.pdf]

[6] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Frequency Determination for Interconnect RLC Extraction," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 288-293, April 2003.