List of works
この検索内の頻出タグ: soc:7 design:5 ai:2 analysis:2 extraction:2 flattening:2 gradient:2 inductance:2 interconnect:2 modeling:2 on-chip:2 resistance:2 si-substrate:2 substrate-aware:2 temperature:2 thermal:2 toward:2 accurately:1 architecture:1 be:1 black-box/white-box:1 can:1 case:1 cases?:1 cells:1 circuit:1 cnn-based:1 composed:1 dynamic:1 edge:1
- 論文誌
- [1] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]
- [2] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]
- 国際会議
- [1] Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, "How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --," Proceedings of Design Automation Conference (DAC), 採録済.
- [2] S. Sombatsiri, J. Yu, M. Hashimoto, and Y. Takeuchi, "A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2019.
- [3] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 107--108, January 2008. [97.pdf]
- [4] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]
- [5] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]