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T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E88-A(12), pp. 3382-3389, December 2005.
ID 12
分類 論文誌
タグ analysis design flattening gradient on-chip soc temperature thermal
表題 (title) On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
表題 (英文)
著者名 (author) T. Sato,J. Ichimiya,N. Ono,K. Hachiya,M. Hashimoto
英文著者名 (author) T. Sato,J. Ichimiya,N. Ono,K. Hachiya,M. Hashimoto
キー (key) T. Sato,J. Ichimiya,N. Ono,K. Hachiya,M. Hashimoto
定期刊行物名 (journal) IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
定期刊行物名 (英文)
巻数 (volume) E88-A
号数 (number) 12
ページ範囲 (pages) 3382-3389
刊行月 (month) 12
出版年 (year) 2005
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル 9.pdf (application/pdf) [一般閲覧可]
BiBTeXエントリ
@article{id12,
         title = {On-chip thermal gradient analysis and temperature flattening for {SoC} design},
        author = {T. Sato and J. Ichimiya and N. Ono and K. Hachiya and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E88-A},
        number = {12},
         pages = {3382-3389},
         month = {12},
          year = {2005},
}