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論文誌

[1] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]

国際会議

[1] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pages 160-163, April 2005. [29.pdf]