: M. Lou, J. Wang, H. Li, Z. Yang, Q. Cheng, J. Li, M. Hashimoto, and L. Lin, Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS, November 2025.
Detail of a work
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| M. Lou, J. Wang, H. Li, Z. Yang, Q. Cheng, J. Li, M. Hashimoto, and L. Lin, "Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS," IEEE Transactions on Circuits and Systems II, 72(11), pp. 1605-1609, November 2025. | |
| ID | 667 |
| 分類 | 論文誌 |
| タグ | 22nm 8t area-efficient bitcell cmos compute-in-memory compute-sram design digital low-power macros |
| 表題 (title) |
Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS |
| 表題 (英文) |
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| 著者名 (author) |
M. Lou,J. Wang,H. Li,Z. Yang,Q. Cheng,J. Li,M. Hashimoto,L. Lin |
| 英文著者名 (author) |
,,,,,,M. Hashimoto, |
| キー (key) |
,,,,,,M. Hashimoto, |
| 定期刊行物名 (journal) |
IEEE Transactions on Circuits and Systems II |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
72 |
| 号数 (number) |
11 |
| ページ範囲 (pages) |
1605-1609 |
| 刊行月 (month) |
11 |
| 出版年 (year) |
2025 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@article{id667,
title = {Area-Efficient and Low-Power {8T} {Compute-SRAM} Bitcell Design for Digital Compute-In-Memory Macros in 22nm {CMOS}},
author = {M. Lou and J. Wang and H. Li and Z. Yang and Q. Cheng and J. Li and M. Hashimoto and L. Lin},
journal = {IEEE Transactions on Circuits and Systems II},
volume = {72},
number = {11},
pages = {1605-1609},
month = {11},
year = {2025},
}
|