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6 件の該当がありました． : このページのURL : HTML

論文誌

[1] Quan Cheng, Longyang Lin, Mingqiang Huang, Qiufeng Li, Zhengke Yang, Liuyao Dai, Hao Yu, Ruilin Zhang, Yu-Jen Chen, Yiyu Shi, and Masanori Hashimoto, "A 22nm End-To-End Edge-AI Processor with Booth-Value-Confined Acceleration and Hardware-Aware Layer-Wise Model Deployment," IEEE Transactions on VLSI Systems, 採録済.

国際会議

[1] Quan Cheng, Haoyuan Li, and Masanori Hashimoto, "Subarashi: a 16nm Sustainable `SNN Processor with Cell-Composition-Based Radiation Resilience and Reconfigurable Array for Harsh Environments," Proceedings of European Solid-State Electronics Research Conference (ESSERC), 採録済.

[2] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), October 2024. [pdf]

[3] T. Hsu, D. Yang, W. Liao, M. Itoh, M. Hashimoto, , and J. Liou, "Processor SER Estimation with ACE Bit Analysis," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2021.

[4] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.

[5] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation," Proceedings of IEEE COOL Chips, page 190, April 2010. [145.pdf]