Search: 簡易 | 詳細 || Language: 英語 | 日本語 || ログイン |

List of works

197 件の該当がありました． : このページのURL : HTML

論文誌: [1] Y. Deng, Y. Watanabe, S. Manabe, W. Liao, M. Hashimoto, S. Abe, M. Tampo, and Y. Miyake, "Impact of Irradiation Side on Muon-Induced Single Event Upsets in 65-nm Bulk SRAMs," IEEE Transactions on Nuclear Science, volume 71, number 4, pages 912-920, April 2024. [pdf]; [2] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing," IEEE Transactions on Nuclear Science, volume 70, number 8, 1652 -- 1657, August 2023. [pdf]; [3] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Vulnerability Estimation of DNN Model Parameters with Few Fault Injections," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E106-A, number 3, pages 523-531, March 2023. [pdf]; [4] A. Lopez, Y. Okoshi, M. Hashimoto, M. Motomura, and J. Yu, "Recurrent Residual Networks Contain Stronger Lottery Tickets," IEEE Access, volume 11, 16588 - 16604, February 2023. [pdf]; [5] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]; [6] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E105-A, number 3, pages 497--508, March 2022. [pdf]; [7] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]; [8] T. Tanaka, W. Liao, M. Hashimoto, and Y. Mitsuyama, "Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior," IEEE Transactions on Nuclear Science, volume 69, number 1, pages 35--42, January 2022. [pdf]; [9] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow," IEEE Transactions on Nuclear Science, volume 68, number 8, pages 1668--1674, August 2021. [pdf]; [10] T. Kato, M. Tampo, S. Takeshita, H. Tanaka, H. Matsuyama, M. Hashimoto, and Y. Miyake, "Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha Particles," IEEE Transactions on Nuclear Science, volume 68, number 7, pages 1436-1444, July 2021. [pdf]; [11] W. Liao, K. Ito, S. Abe, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 68, number 6, pages 1228-1234, June 2021. [pdf]; [12] R. Shirai, Y. Itoh, and M. Hashimoto, "Make It Trackable: an Instant Magnetic Tracking System with Coil-Free Tiny Trackers," IEEE Access, volume 9, 26616 - 26632, February 2021. [pdf]; [13] T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, volume 74, pages 19--31, September 2020. [pdf]; [14] T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, and A. Sato, "Irradiation Test of 65 nm Bulk SRAMs with DC Muon Beam at RCNP MuSIC Facility," IEEE Transactions on Nuclear Science, volume 67, number 7, 1555 -- 1559, July 2020. [pdf]; [15] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs," IEEE Transactions on Nuclear Science, volume 67, number 7, 1566 -- 1572, July 2020. [pdf]; [16] J. Kuroda, S. Manabe, Y. Watanabe, K. Ito, W. Liao, M. Hashimoto, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Measurement of Single-Event Upsets in 65-nm SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF," IEEE Transactions on Nuclear Science, volume 67, number 7, 1599 -- 1605, July 2020. [pdf]; [17] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, volume 69, pages 161--179, November 2019. [pdf]; [18] S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, and Y. Watanabe, "Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs," IEEE Transactions on Nuclear Science, volume 66, number 7, 1374 -- 1380, July 2019. [pdf]; [19] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 867--877, July 2019. [pdf]; [20] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 66, number 7, 1390 -- 1397, July 2019. [pdf]; [21] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, and S. Abe, "Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs," IEEE Transactions on Nuclear Science, volume 66, number 7, 1398 -- 1403, July 2019. [pdf]; [22] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture," IEEE Embedded Systems Letters, volume 10, number 4, 119 -- 122, December 2018. [desc]; [23] H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, volume 26, number 12, pages 2723--2736, December 2018. [pdf]; [24] Y. Masuda, T. Onoye, and M. Hashimoto, "Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving," IEEE Transactions on VLSI Systems, volume 26, number 11, pages 2217--2229, November 2018. [pdf]; [25] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, and Y. Miyake, "Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs," IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1742--1749, August 2018. [pdf]; [26] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65-nm Bulk SRAMs," IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1734--1741, August 2018. [pdf]; [27] Y. Masuda, T. Onoye, and M. Hashimoto, "Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E100-A, number 7, pages 1452--1463, July 2017. [pdf]; [28] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 12, pages 2607--2613, December 2015.; [29] D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, "Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 7, pages 1467--1474, July 2015. [221.pdf]; [30] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014. [210.pdf]; [31] D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, and M. Hashimoto, "Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2373--2382, December 2014. [209.pdf]; [32] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1468--1482, July 2014. [201.pdf]; [33] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1483--1491, July 2014. [202.pdf]; [34] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1461--1467, July 2014. [200.pdf]; [35] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, volume 21, number 12, 2165 -- 2178, December 2013. [177.pdf]; [36] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems, volume E96-D, number 8, pages 1624--1631, August 2013. [191.pdf]; [37] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling," IEEE Transactions on Information Forensics and Security, volume 8, number 8, pages 1331--1342, August 2013. [190.pdf]; [38] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement," IEEE Transactions on Nuclear Science, volume 60, number 4, pages 2630--2634, August 2013. [180.pdf]; [39] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), volume 10, number 5, April 2013. [184.pdf]; [40] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Supply Noise Suppression by Triple-Well Structure," IEEE Transactions on VLSI Systems, volume 21, number 4, pages 781--785, April 2013. [169.pdf]; [41] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013. [182.pdf]; [42] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012. [175.pdf]; [43] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2220--2225, December 2012. [172.pdf]; [44] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 20, number 2, pages 333--343, February 2012. [155.pdf]; [45] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2545--2553, December 2011. [166.pdf]; [46] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011. [159.pdf]; [47] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2417--2423, December 2010. [149.pdf]; [48] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 18, number 7, pages 1118--1129, July 2010. [130.pdf]; [49] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]; [50] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3094--3102, December 2009. [128.pdf]; [51] Y. Ogasahara, M. Hashimoto, and T. Onoye, "All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform," IEEE Journal of Solid-State Circuits, volume 44, number 6, pages 1745--1755, June 2009. [124.pdf]; [52] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Trans. on Electronics, volume E92-C, number 2, pages 281--285, February 2009. [117.pdf]; [53] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3461-3464, December 2008. [111.pdf]; [54] Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Area-Efficient Reconfigurable Architecture for Media Processing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3651-3662, December 2008. [114.pdf]; [55] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects," IEEE Journal of Solid-State Circuits, volume 43, number 3, pages 718--728, March 2008. [99.pdf]; [56] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Transactions on Circuits and Systems II, volume 54, number 10, pages 868--872, October 2007. [94.pdf]; [57] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 724--731, April 2007. [80.pdf]; [58] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積もりの容易化," 情報処理学会論文誌, volume 47, number 6, pages 1665-1673, 2006年6月.; [59] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]; [60] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶のための配線容量抽出手法," 情報処理学会論文誌, volume 46, number 6, pages 1395-1403, 2005年6月.; [61] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 23, number 4, pages 498-508, April 2004. [20.pdf]; [62] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 3204-3207, December 2003. [15.pdf]; [63] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, "遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会論文誌, volume 44, number 5, pages 1301-1310, 2003年5月. [21.pdf]
国際会議: [1] R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, Y. Yamaguchi, D. Tomono, and F. Minato, "In-Beam Activation Measurement of Muon Nuclear Capture Reaction on Si Isotopes," The workshop on frontier nuclear studies with gamma-ray spectrometer arrays (gamma24), March 2024.; [2] R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, Y. Yamaguchi, D. Tomono, and F. Minato, "Muon Nuclear Capture Reaction on 28,29,30si," 2023 Fall meeting of APS DNP and JPS, November 2023.; [3] Y. Gomi, K. Takami, R. Mizuno, M. Niikura, Y. Deng, S. Kawase, Y. Watanabe, S. Abe, W. Liao, M. Tampo, I. Umegaki, S. Takeshita, K. Shimomura, Y. Miyake, and M. Hashimoto, "Muon-Induced SEU Cross Sections of 12-nm FinFET and 28-nm Planar SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2023.; [4] M. Niikura, R. Mizuno, S. Manabe, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, A. Hillier, N. Kawamura, Y. Kawashima, S. Kawase, T. Kawata, K. Kitafuji, F. Minato, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, M. Tampo, D. Tomono, I. Umegaki, Y. Yamaguchi, and Y. Watanabe, "Nuclear Physics for Muon-Induced Soft Error," Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis, August 2023.; [5] R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, and I. Umegaki, "Study of Muon Capture Reaction on Si Via In-Beam Muon Activation," Advances in Radioactive Isotope Science (ARIS), June 2023.; [6] K. Takami, Y. Gomi, S. Abe, W. Liao, S. Manabe, T. Matsumoto, and M. Hashimoto, "Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons," Proceedings of International Reliability Physics Symposium (IRPS), March 2023. [pdf]; [7] R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, and I. Umegaki, "Study of Muon Capture Reaction on Si Via In-Beam Muon Activation," Topical Workshops on Modern Aspects of Nuclear Structure, February 2023.; [8] R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, and I. Umegaki, "Measurement of Muon-Induced Nuclear Transmutation for Si Isotopes," Trans-scale Quantum Science Institute, November 2022.; [9] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.; [10] M. Hashimoto, Y. Zhang, and K. Ito, "Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards," Proceedings of International Conference on Solid State Devices and Materials (SSDM), September 2022.; [11] D. Fujimoto, Y. Kim, Y. Hayashi, N. Homma, M. Hashimoto, T. Sato, and J.-L. Danger, "SASIMI: Evaluation Board for EM Information Leakage from Large Scale Cryptographic Circuits," IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity, August 2022. [pdf]; [12] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections," Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 60-63, March 2022. [pdf]; [13] T. Tanaka, M. Hashimoto, and Y. Takeuchi, "Linear Programming Based Reliable Software Performance Model Construction with Noisy CPU Performance Counter Values," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), March 2021.; [14] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]; [15] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]; [16] T. Kato, M. Tampo, S. Takeshita, Y. Miyake, H Tanaka, and M. Hashimoto, "Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles," IEEE Nuclear and Space Radiation Effects Conference (NSREC), November 2020.; [17] Y. Zhang, K. Ito, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.; [18] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.; [19] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020.; [20] S. Abe, T. Sato, J. Kuroda, S. Manabe, Y. Watanabe, W. Liao, K. Ito, M. Hashimoto, M. Harada, K. Oikawa, and Y. Miyake, "Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets," Proceedings of International Symposium on Reliability Physics (IRPS), April 2020. [pdf]; [21] W. Liao, K. Ito, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2020. [pdf]; [22] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]; [23] Z. Yan, Y. Shi, W. Liao, M. Hashimoto, X. Zhou, and C. Zhuo, "When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020. [pdf]; [24] S. Sombatsiri, J. Yu, M. Hashimoto, and Y. Takeuchi, "A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2019.; [25] T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, and A. Sato, "Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.; [26] K. Ito, W. Liao, M. Hashimoto, J. Kuroda, S. Manabe, Y. Watanabe, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.; [27] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Impact of Incident Angle on Negative Muon-Induced SEU Cross Section of 65-nm Bulk SRAM," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.; [28] J. Kuroda, S. Manabe, Y. Watanabe, K. Ito, W. Liao, M. Hashimoto, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Measurement of Single-Event Upsets in 65-nm Bulk SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.; [29] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]; [30] J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, "Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP," Design Automation Conference, Designer/IP Track, June 2019.; [31] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2019. [pdf]; [32] Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto, "Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]; [33] M. Hashimoto, W. Liao, S. Manabe, and Y. Watanabe, "Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2018. [pdf]; [34] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, and S. Abe, "Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.; [35] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.; [36] S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, and Y. Watanabe, "Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.; [37] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]; [38] K.-W. Lin, M. Hashimoto, and Y.-L. Li, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties," Proceedings of International Symposium on Quality Electronic Design (ISQED), March 2018. [pdf]; [39] M. Hashimoto and Y. Masuda, "MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018. [pdf]; [40] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [pdf]; [41] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2017.; [42] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Momentum and Supply Voltage Dependencies of SEUs Induced by Low-Energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2017.; [43] M. Hashimoto, R. Shirai, Y. Itoh, and T. Hirose, "Toward Real-Time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)," Proceedings of IEEE International Conference on ASIC, pages 1087--1091, October 2017. [pdf]; [44] K.-W. Lin, Y.-L. Li, and M. Hashimoto, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles," Proceedings of IEEE Intelligent Vehicles Symposium (IV), pages 1465--1470, June 2017. [pdf]; [45] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices," Proceedings of IEEE Wireless Power Transfer Conference (WPTC), May 2017. [pdf]; [46] K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, and M. Hashimoto, "GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction," Proceedings of International Conference on Intelligent User Interfaces (IUI), pages 173--178, March 2017. [pdf]; [47] Y. Masuda, M. Hashimoto, and T. Onoye, "Critical Path Isolation for Time-To-Failure Extension and Lower Voltage Operation," Proceedings of International Conference on Computer-Aided Design (ICCAD), November 2016. [230.pdf]; [48] Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, and M. Hashimoto, "Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [232.pdf]; [49] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [pdf]; [50] H.-Y. Su, B.-S. Wang, S.-Y. Hsieh, Y.-L. Li, I-H. Wu, C.-C. Wu, W.-C. Shih, H. Onodera, and M. Hashimoto, "Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2016.; [51] S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, and M. Hashimoto, "Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2016. [pdf]; [52] H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, and T. Sugibayashi, "Novel Processor Architecture for Onboard Infrared Sensors (Invited)," Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, volume 9973, August 2016.; [53] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2016. [pdf]; [54] Y. Masuda, M. Hashimoto, and T. Onoye, "Hardware-Simulation Correlation of Timing Error Detection Performance of Software-Based Error Detection Mechanisms," Proceedings of International On-Line Testing Symposium (IOLTS), pages 84--89, July 2016. [228.pdf]; [55] Y. Masuda, M. Hashimoto, and T. Onoye, "Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.; [56] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.; [57] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015. [225.PDF]; [58] Y. Masuda, M. Hashimoto, and T. Onoye, "Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise," Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 315-322, November 2015. [224.pdf]; [59] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," Proceedings of International Test Conference (ITC), October 2015. [223.pdf]; [60] Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, and M. Hashimoto, "A Wireless Power Transfer System for Small-Sized Sensor Applications," Proceedings of International Conference on Solid State Devices and Materials (SSDM), pages 154--155, September 2015.; [61] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.; [62] S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, "3D Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method," Proceedings of Virtual Reality Conference (VR), March 2015. [218.pdf]; [63] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 731--736, January 2015. [214.pdf]; [64] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015. [213.pdf]; [65] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, and T. Onoye, "Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2013. [199.pdf]; [66] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313--316, November 2013. [196.pdf]; [67] Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, "Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator," Proceedings of IEEE European Test Symposium (ETS), pages 106--111, May 2013. [186.pdf]; [68] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012. [174.pdf]; [69] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.; [70] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2012. [170.pdf]; [71] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2012.; [72] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "SET Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects," Proceedings of International Reliability Physics Symposium (IRPS), April 2012. [168.PDF]; [73] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 189--194, September 2011. [162.pdf]; [74] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011. [163.pdf]; [75] T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "NBTI Mitigation by Giving Random Scan-In Vectors During Standby Mode," Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pages 152--161, September 2011.; [76] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing," Proceedings of International Reliability Physics Symposium (IRPS), pages 253--257, April 2011. [156.PDF]; [77] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.; [78] Y. Takai, M. Hashimoto, and T. Onoye, "Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation," Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pages 213--216, October 2010. [146.pdf]; [79] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling," Proceedings of International Workshop on Information Security Applications (WISA), pages 107-121, August 2010.; [80] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010. [140.PDF]; [81] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO," Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010. [139.pdf]; [82] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 646--651, March 2010. [137.pdf]; [83] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 839--844, March 2010. [138.pdf]; [84] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 361 -- 362, January 2010. [131.pdf]; [85] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient VLSI Architecture for Signal Processing," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009. [142.pdf]; [86] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 215--218, September 2009. [127.pdf]; [87] K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 51--56, August 2009. [125.pdf]; [88] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009. [133.pdf]; [89] Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 236--241, March 2009.; [90] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.; [91] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009. [115.pdf]; [92] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 266-271, January 2009. [116.pdf]; [93] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 397--400, November 2008. [109.pdf]; [94] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," Proceedings of Workshop on Test Structure Design for Variability Characterization, November 2008.; [95] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008. [123.pdf]; [96] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 3--8, August 2008. [106.pdf]; [97] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI), pages 387--390, May 2008. [104.pdf]; [98] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 107--108, January 2008. [97.pdf]; [99] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 233-237, October 2007.; [100] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," Proceedings of 37th European Solid-State Device Research Conference (ESSDERC), pages 115--118, September 2007. [92.pdf]; [101] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 783--786, September 2007. [90.pdf]; [102] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects," In Proceedings of IEEE International Conference on Computer Design (ICCD), pages 70-75, October 2006. [23.pdf]; [103] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 721-724, September 2006. [24.pdf]; [104] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC),, pages 861-864, September 2006. [25.pdf]; [105] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Delay Variation Due to Inductive Coupling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 305-308, September 2005. [26.pdf]; [106] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pages 160-163, April 2005. [29.pdf]; [107] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 169-175, November 2003. [42.pdf]; [108] M. Hashimoto, Y. Yamada, and H. Onodera, "Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 18-23, April 2003. [45.pdf]; [109] Y. Yamada, M. Hashimoto, and H. Onodera, "Slew Calculation Against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 280-287, April 2003.; [110] T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, "Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 149-155, January 2003. [40.pdf]; [111] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," In Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS), pages 283-287, June 2002.
国内会議(査読付き): [1] Y. Sun, R. Doi, and M. Hashimoto, "Rc Extraction-Free Wiring Delay Analysis Focusing on Number of On-State Switches for Via-Switch Fpga," 情報処理学会DAシンポジウム, August 2019.; [2] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測," 第19回回路とシステム(軽井沢)ワークショップ, pages 5-10, 2006年4月. [73.pdf]; [3] 林宙輝, 橋本昌宜, 小野寺秀俊, "セルベース設計環境を用いた高性能データパス設計法の検討," 情報処理学会DAシンポジウム, pages 113-118, 2002年7月.; [4] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会DAシンポジウム, pages 149-154, 2002年7月.; [5] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスが配線遅延に及ぼす影響の定量的評価方法," 第15回回路とシステム(軽井沢)ワークショップ, pages 493-498, 2002年4月.
研究会・全国大会等: [1] R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, and D. Tomono, "ミューオン原子核捕獲反応による生成核分岐比の測定," 第12回停止・低速RIビームを用いた核分光研究会 (12th SSRI), September 2023.; [2] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.; [3] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," Work in Progress Session, Design Automation Conference (DAC), June 2016.; [4] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," 電子情報通信学会 VLSI設計技術研究会, March 2015.; [5] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史、尾上孝雄, "電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現," 電子情報通信学会集積回路研究会,, number ICD2006-174, 2007年1月.; [6] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測," 電子情報通信学会集積回路研究会, number ICD2006-173, 2007年1月.; [7] 小笠原泰弘, 新開健一, 榎並孝司, 阿部慎也, 二宮進有, 橋本昌宜, "ナノメートル世代のVLSIタイミング設計技術の研究," 第10回システムLSIワークショップ, pages 195-198, 2006年11月.; [8] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "誘導性・容量性クロストークノイズによる遅延変動の測定と評価," 電子情報通信学会集積回路研究会, number ICD2005-74, 2005年8月.; [9] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶設計のための配線容量抽出手法," 電子情報通信学会 VLSI設計技術研究会(デザインガイア), number VLD2004-64, 2004年12月.; [10] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶に適した配線間容量抽出の検討," 2004年電子情報通信学会ソサイエティ大会講演論文集, number A-1-16, 2004年9月.; [11] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "静的遅延解析のための等価ゲート入力波形導出法　--VDSMプロセスに起因する波形歪みへの対応--," 情報処理学会システムLSI設計技術研究会, number 2003-SLDM-108-20, pages 111-116, 2003年1月.; [12] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "容量性クロストークを考慮した高精度タイミング解析に関する研究," 平成14年度情報処理学会関西支部支部大会 VLSI研究会, number C-3, pages 113-114, 2002年11月.; [13] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスに起因する配線遅延変動の統計的予測手法," 2002年電子情報通信学会ソサイエティ大会講演論文集, number TA-2-4, pages 247-248, 2002年9月.; [14] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "ゲート出力波形導出時の誤差要因とその影響の評価," 2002年電子情報通信学会総合大会講演論文集, number A-3-3, page 82, 2002年3月.
著書: [1] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Atomic Switch FPGA: Application for IoT Sensing Systems in Space," Book Chapter, Atomic Switch, Springer, March 2020.; [2] E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, and M. Sugihara, "Radiation-Induced Soft Errors," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.; [3] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, and M. Tada, "Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.; [4] T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, and J. Yao, "Time-Dependent Degradation in Device Characteristics and Countermeasures by Design," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.