この検索内の頻出タグ: device-parameter^:2 extracting^:2 ro-based^:2 sensors^:2 variations^:2 analysis^:1 clock^:1 considering^:1 due^:1 jitter^:1 noise^:1 power^:1 process^:1 skew^:1 statistical^:1 supply^:1 timing^:1 variation^:1

17 件の該当がありました． : このページのURL : HTML

論文誌

[1] K. Shinkai, M. Hashimoto, and T. Onoye, "A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations," Integration, the VLSI Journal, volume 46, number 4, pages 345--358, September 2013. [179.pdf]

[2] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with RO-Based Sensors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2537--2544, December 2011. [165.pdf]

[3] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2399--2408, December 2010. [148.pdf]

[4] K. Shinkai, M. Hashimoto, and T. Onoye, "Prediction of Self-Heating in Short Intra-Block Wires," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 3, pages 583--594, March 2010. [135.pdf]

国際会議

[1] Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, "Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator," Proceedings of IEEE European Test Symposium (ETS), pages 106--111, May 2013. [186.pdf]

[2] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with RO-Based Sensors," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 13--18, March 2011.

[3] K. Shinkai and M. Hashimoto, "Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 683--688, January 2011. [152.pdf]

[4] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," ACM Great Lake Symposium on VLSI (GLSVLSI), pages 197--202, May 2010. [143.pdf]

[5] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 41--46, March 2010.

[6] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 89--94, March 2010.

[7] K. Shinkai and M. Hashimoto, "A Gate Delay Model Over Wide-Range of Process and Environmental Variability," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 79--84, February 2009.

[8] K. Shinkai, M. Hashimoto, and T. Onoye, "Future Prediction of Self-Heating in Short Intra-Block Wires," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 660-665, March 2007. [82.PDF]

[9] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 47-53, November 2006. [22.pdf]

[10] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations," In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 59-64, February 2006.

国内会議(査読付き)

[1] 新開健一, 橋本昌宜, 黒川敦, 尾上孝雄, "電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル," 第19回 回路とシステム(軽井沢)ワークショップ, pages 559-564, 2006年4月. [75.pdf]

研究会・全国大会等

[1] 小笠原泰弘, 新開健一, 榎並孝司, 阿部慎也, 二宮進有, 橋本昌宜, "ナノメートル世代のVLSIタイミング設計技術の研究," 第10回システムLSIワークショップ, pages 195-198, 2006年11月.

[2] 新開健一, 橋本昌宜, 尾上孝雄, "短距離ブロック内配線の自己発熱問題の将来予測," 2006年電子情報通信学会ソサイエティ大会講演論文集, number A-3-14, 2006年9月. [72.pdf]