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論文誌
[1] Y. Deng, Y. Watanabe, S. Manabe, W. Liao, M. Hashimoto, S. Abe, M. Tampo, and Y. Miyake, "Impact of Irradiation Side on Muon-Induced Single Event Upsets in 65-Nm Bulk SRAMs," IEEE Transactions on Nuclear Science, 採録済. [pdf]
[2] Q. Cheng, M. Huang, C. Man, A. Shen, L. Dai, H. Yu, and M. Hashimoto, "Reliability Exploration of System-On-Chip with Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, volume 70, number 10, 3978 -- 3991, October 2023. [pdf]
[3] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing," IEEE Transactions on Nuclear Science, volume 70, number 8, 1652 -- 1657, August 2023. [pdf]
[4] Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, "A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier," IEEE Transactions on Circuits and Systems II, volume 70, number 6, 2246 - 2250, June 2023. [pdf]
[5] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Vulnerability Estimation of DNN Model Parameters with Few Fault Injections," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E106-A, number 3, pages 523-531, March 2023. [pdf]
[6] H. Awano and M. Hashimoto, "B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA," Integration, the VLSI Journal, volume 89, pages 1-8, March 2023. [pdf]
[7] A. Lopez, Y. Okoshi, M. Hashimoto, M. Motomura, and J. Yu, "Recurrent Residual Networks Contain Stronger Lottery Tickets," IEEE Access, volume 11, 16588 - 16604, February 2023. [pdf]
[8] G. L. Zhang, B. Li, X. Huang, X. Yin, C. Zhuo, M. Hashimoto, and U. Schlichtmann, "Virtualsync+: Timing Optimization with Virtual Synchronization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 41, number 12, pages 5526-5540, December 2022. [pdf]
[9] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]
[10] X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Via-Switch FPGA: 65nm CMOS Implementation and Evaluation," IEEE Journal of Solid-State Circuits, volume 57, number 7, pages 2250-2262, July 2022. [pdf]
[11] D. Liang, J. Shiomi, N. Miura, M. Hashimoto, and H. Awano, "A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter," IEICE Trans. on Information and Systems, volume 105-D, number 7, pages 1273--1282, July 2022. [pdf]
[12] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E105-A, number 3, pages 497--508, March 2022. [pdf]
[13] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , and M. Hashimoto, "Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 105-A, number 3, pages 509--517, March 2022. [pdf]
[14] T. Tanaka, W. Liao, M. Hashimoto, and Y. Mitsuyama, "Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior," IEEE Transactions on Nuclear Science, volume 69, number 1, pages 35--42, January 2022. [pdf]
[15] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow," IEEE Transactions on Nuclear Science, volume 68, number 8, pages 1668--1674, August 2021. [pdf]
[16] T. Kato, M. Tampo, S. Takeshita, H. Tanaka, H. Matsuyama, M. Hashimoto, and Y. Miyake, "Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha Particles," IEEE Transactions on Nuclear Science, volume 68, number 7, pages 1436-1444, July 2021. [pdf]
[17] W. Liao, K. Ito, S. Abe, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 68, number 6, pages 1228-1234, June 2021. [pdf]
[18] R. Shirai, Y. Itoh, and M. Hashimoto, "Make It Trackable: an Instant Magnetic Tracking System with Coil-Free Tiny Trackers," IEEE Access, volume 9, 26616 - 26632, February 2021. [pdf]
[19] R. Doi, X. Bai, T. Sakamoto, and M. Hashimoto, "A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 103-A, number 12, pages 1447--1455, December 2020. [pdf]
[20] J. Chen and M. Hashimoto, "A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 10, number 11, 1769 -- 1781, November 2020. [pdf]
[21] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-Switch Crossbar Based FPGA," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 39, number 10, pages 2572--2587, October 2020. [pdf]
[22] T. Cheng, Y. Masuda, J. Chen, J. Yu, and M. Hashimoto, "Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training," Integration, the VLSI Journal, volume 74, pages 19--31, September 2020. [pdf]
[23] T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, and A. Sato, "Irradiation Test of 65 nm Bulk SRAMs with DC Muon Beam at RCNP MuSIC Facility," IEEE Transactions on Nuclear Science, volume 67, number 7, 1555 -- 1559, July 2020. [pdf]
[24] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs," IEEE Transactions on Nuclear Science, volume 67, number 7, 1566 -- 1572, July 2020. [pdf]
[25] J. Kuroda, S. Manabe, Y. Watanabe, K. Ito, W. Liao, M. Hashimoto, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Measurement of Single-Event Upsets in 65-nm SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF," IEEE Transactions on Nuclear Science, volume 67, number 7, 1599 -- 1605, July 2020. [pdf]
[26] T. Kato, M. Hashimoto, and H. Matsuyama, "Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs with Comparison to 20-nm Planar SRAMs," IEEE Transactions on Nuclear Science, volume 67, number 7, 1485 -- 1493, July 2020. [pdf]
[27] R. Shirai and M. Hashimoto, "DC Magnetic Field Based 3D Localization with Single Anchor Coil," IEEE Sensors Journal, volume 20, number 7, 3902 -- 3913, April 2020. [pdf]
[28] M. Hashimoto, K. Kobayashi, J. Furuta, S. Abe, and Y. Watanabe, "Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)," Integration, the VLSI Journal, volume 69, pages 161--179, November 2019. [pdf]
[29] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]
[30] N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA," IEEE Transactions on Electron Devices, volume 66, number 8, pages 3331--3336, August 2019. [pdf]
[31] T. Nakayama and M. Hashimoto, "Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 914--917, July 2019. [pdf]
[32] S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, and Y. Watanabe, "Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs," IEEE Transactions on Nuclear Science, volume 66, number 7, 1374 -- 1380, July 2019. [pdf]
[33] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 867--877, July 2019. [pdf]
[34] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 66, number 7, 1390 -- 1397, July 2019. [pdf]
[35] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, and S. Abe, "Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs," IEEE Transactions on Nuclear Science, volume 66, number 7, 1398 -- 1403, July 2019. [pdf]
[36] W. Liao and M. Hashimoto, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, volume E102-C, number 4, pages 296--302, April 2019. [pdf]
[37] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture," IEEE Embedded Systems Letters, volume 10, number 4, 119 -- 122, December 2018. [desc]
[38] H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, and M. Hashimoto, "Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars," IEEE Transactions on VLSI Systems, volume 26, number 12, pages 2723--2736, December 2018. [pdf]
[39] Y. Masuda, T. Onoye, and M. Hashimoto, "Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving," IEEE Transactions on VLSI Systems, volume 26, number 11, pages 2217--2229, November 2018. [pdf]
[40] K. Mitsunari, J. Yu, T. Onoye, and M. Hashimoto, "Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E101-A, number 9, pages 1298--1307, September 2018. [pdf]
[41] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, and Y. Miyake, "Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs," IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1742--1749, August 2018. [pdf]
[42] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65-nm Bulk SRAMs," IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1734--1741, August 2018. [pdf]
[43] B. Li, M. Hashimoto, and U. Schlichtmann, "From Process Variations to Reliability: a Survey of Timing of Digital Circuits in the Nanometer Era (Invited)," IPSJ Transactions on System LSI Design Methodology, volume 11, pages 2--15, February 2018.
[44] R. Doi, M. Hashimoto, and T. Onoye, "An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication," International Journal of Embedded Systems, volume 10, number 1, pages 22-31, January 2018.
[45] Y. Masuda, T. Onoye, and M. Hashimoto, "Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E100-A, number 7, pages 1452--1463, July 2017. [pdf]
[46] C.-C. Hsu, M. Hashimoto, and P.-H. Lin, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Integration, the VLSI Journal, volume 58, pages 236--244, June 2017. [233.pdf]
[47] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 12, pages 2607--2613, December 2015.
[48] D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, "Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 7, pages 1467--1474, July 2015. [221.pdf]
[49] T. Shinada, M. Hashimoto, and T. Onoye, "Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes," Analog Integrated Circuits and Signal Processing, May 2015. [220.pdf]
[50] S. Hirokawa, R. Harada, M. Hashimoto, and T. Onoye, "Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs," IEEE Transactions on Nuclear Science, volume 62, number 2, pages 420--427, April 2015. [219.pdf]
[51] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Exploring Well-Configurations for Minimizing Single Event Latchup," IEEE Transactions on Nuclear Science, volume 61, number 6, pages 3282--3289, December 2014. [211.pdf]
[52] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014. [210.pdf]
[53] T. Amaki, M. Hashimoto, and T. Onoye, "A Process and Temperature Tolerant Oscillator-Based True Random Number Generator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2393--2399, December 2014. [208.pdf]
[54] D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, and M. Hashimoto, "Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2373--2382, December 2014. [209.pdf]
[55] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1468--1482, July 2014. [201.pdf]
[56] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1483--1491, July 2014. [202.pdf]
[57] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1461--1467, July 2014. [200.pdf]
[58] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014. [185.pdf]
[59] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013. [197.pdf]
[60] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4232--4237, December 2013. [198.pdf]
[61] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, volume 21, number 12, 2165 -- 2178, December 2013. [177.pdf]
[62] K. Shinkai, M. Hashimoto, and T. Onoye, "A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations," Integration, the VLSI Journal, volume 46, number 4, pages 345--358, September 2013. [179.pdf]
[63] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems, volume E96-D, number 8, pages 1624--1631, August 2013. [191.pdf]
[64] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling," IEEE Transactions on Information Forensics and Security, volume 8, number 8, pages 1331--1342, August 2013. [190.pdf]
[65] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement," IEEE Transactions on Nuclear Science, volume 60, number 4, pages 2630--2634, August 2013. [180.pdf]
[66] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), volume 10, number 5, April 2013. [184.pdf]
[67] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Supply Noise Suppression by Triple-Well Structure," IEEE Transactions on VLSI Systems, volume 21, number 4, pages 781--785, April 2013. [169.pdf]
[68] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013. [182.pdf]
[69] T. Amaki, M. Hashimoto, and T. Onoye, "Jitter Amplifier for Oscillator-Based True Random Number Generator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E96-A, number 3, pages 684--696, March 2013. [181.pdf]
[70] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on MINIMAX Sampling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E96-A, number 2, pages 459--468, February 2013. [178.pdf]
[71] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012. [175.pdf]
[72] T. Enami, T. Sato, and M. Hashimoto, "Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2261--2271, December 2012. [171.pdf]
[73] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2220--2225, December 2012. [172.pdf]
[74] S. Kimura, M. Hashimoto, and T. Onoye, "A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2292--2300, December 2012. [173.pdf]
[75] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 20, number 2, pages 333--343, February 2012. [155.pdf]
[76] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2545--2553, December 2011. [166.pdf]
[77] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with RO-Based Sensors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2537--2544, December 2011. [165.pdf]
[78] T. Okumura and M. Hashimoto, "Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 10, pages 1948--1953, October 2011. [164.pdf]
[79] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011. [159.pdf]
[80] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, "An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion," IEEE Transactions on Circuits and Systems II, volume 58, number 5, pages 299--303, May 2011. [158.pdf]
[81] S. Ninomiya and M. Hashimoto, "Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2441--2446, December 2010. [150.pdf]
[82] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2417--2423, December 2010. [149.pdf]
[83] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in STA under Dynamic Power Supply Noise," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2447--2455, December 2010. [151.pdf]
[84] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2399--2408, December 2010. [148.pdf]
[85] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 18, number 7, pages 1118--1129, July 2010. [130.pdf]
[86] T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, and M. Hashimoto, "Impact of Self-Heating in Wire Interconnection on Timing," IEICE Trans. on Electronics, volume E93-C, number 3, pages 388--392, March 2010. [136.pdf]
[87] K. Shinkai, M. Hashimoto, and T. Onoye, "Prediction of Self-Heating in Short Intra-Block Wires," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 3, pages 583--594, March 2010. [135.pdf]
[88] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]
[89] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3094--3102, December 2009. [128.pdf]
[90] T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, "An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3016--3023, December 2009. [129.pdf]
[91] A. Kurokawa, T. Sato, T. Kanamoto, and M. Hashimoto, "Interconnect Modeling: a Physical Design Perspective (Invited)," IEEE Transactions on Electron Devices, volume 56, number 9, pages 1840--1851, September 2009. [126.pdf]
[92] Y. Ogasahara, M. Hashimoto, and T. Onoye, "All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform," IEEE Journal of Solid-State Circuits, volume 44, number 6, pages 1745--1755, June 2009. [124.pdf]
[93] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, 541 - 553, April 2009. [118.pdf]
[94] T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, and T. Sato, "Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 92-A, number 4, pages 990--997, April 2009. [119.pdf]
[95] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Trans. on Electronics, volume E92-C, number 2, pages 281--285, February 2009. [117.pdf]
[96] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3461-3464, December 2008. [111.pdf]
[97] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3481-3487, December 2008. [112.pdf]
[98] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3474-3480, December 2008. [113.pdf]
[99] Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, and I. Shirakawa, "Area-Efficient Reconfigurable Architecture for Media Processing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3651-3662, December 2008. [114.pdf]
[100] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," IEICE Trans. on Information and Systems, volume E91-D, number 3, pages 655--660, March 2008. [101.pdf]
[101] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects," IEEE Journal of Solid-State Circuits, volume 43, number 3, pages 718--728, March 2008. [99.pdf]
[102] M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of LCD Driver Circuit for Technology Migration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2712--2717, December 2007. [96.pdf]
[103] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2661-2668, December 2007. [95.pdf]
[104] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Transactions on Circuits and Systems II, volume 54, number 10, pages 868--872, October 2007. [94.pdf]
[105] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling," IEICE Trans. on Electronics, volume E90-C, number 6, pages 1267-1273, June 2007. [88.pdf]
[106] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 724--731, April 2007. [80.pdf]
[107] H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, and M. Hashimoto, "Proposal of Metrics for SSTA Accuracy Evaluation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 4, pages 808--814, April 2007. [81.pdf]
[108] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3538-3545, December 2006. [1.pdf]
[109] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3585-3593, December 2006. [2.pdf]
[110] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006. [3.pdf]
[111] T. Sato, J. Ichimiya, N. Ono, and M. Hashimoto, "On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3491-3499, December 2006. [4.pdf]
[112] T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, and M. Hashimoto, "Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3666-3670, December 2006. [5.pdf]
[113] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積もりの容易化," 情報処理学会論文誌, volume 47, number 6, pages 1665-1673, 2006年6月.
[114] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pp.3375-3381, December 2005. [6.pdf]
[115] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3564-3572, December 2005. [7.pdf]
[116] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment for Minimizing Supply Voltage Drop," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A,, number 12, pages 3429-3436, December 2005. [8.pdf]
[117] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005. [9.pdf]
[118] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]
[119] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶のための配線容量抽出手法," 情報処理学会論文誌, volume 46, number 6, pages 1395-1403, 2005年6月.
[120] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 885-891, April 2005. [11.pdf]
[121] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL," IEICE Trans. on Electronics, volume E88-C, number 3, pages 437-444, March 2005. [89.pdf]
[122] M. Hashimoto and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E87-A, number 12, pages 3251-3257, December 2004. [12.pdf]
[123] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 23, number 4, pages 498-508, April 2004. [20.pdf]
[124] M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Estimation for Generic RC Trees," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2965-2973, December 2003. [13.pdf]
[125] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2942-2951, December 2003. [14.pdf]
[126] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 3204-3207, December 2003. [15.pdf]
[127] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜, "遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会論文誌, volume 44, number 5, pages 1301-1310, 2003年5月. [21.pdf]
[128] M. Hashimoto and H. Onodera, "Increase in Delay Uncertainty by Performance Optimization," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 12, pages 2799-2802, December 2002. [16.pdf]
[129] 土谷亮, 橋本昌宜, 小野寺秀俊, "VLSI配線の伝送線路特性を考慮した駆動力決定手法," 情報処理学会論文誌, volume 43, number 5, pages 1338--1347, 2002年5月. [63.pdf]
[130] M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E84-A, number 11, pages 2769-2777, November 2001. [17.pdf]
[131] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E83-A, number 12, pages 2558-2568, December 2000. [18.pdf]
[132] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法," 情報処理学会論文誌, volume 40, number 4, pages 1707-1716, 1999年4月.
[133] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E82-A, number 1, pages 159-166, January 1999. [19.pdf]
国際会議
[1] K. Suemitsu, K. Matsuoka, T. Sato, and M. Hashimoto, "Logic Locking Over TFHE for Securing User Data and Algorithms," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 採録済.
[2] C. Kawano and M. Hashimoto, "Performance Comparison of Memristor Crossbar-Based Analog and Fpga-Based Digital Weight-Memory-Less Neural Networks," Proceedings of IEEE International Conference on Rebooting Computing (ICRC), 採録済.
[3] K. Takeuchi, T. Kato, and M. Hashimoto, "An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs," Proceedings of International Symposium on Reliability Physics (IRPS), 採録済.
[4] Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, "How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --," Proceedings of Design Automation Conference (DAC), 採録済.
[5] T. Matsumoto, R. Shirai, and M. Hashimoto, "A Proof-Of-Concept Prototyping of Reservoir Computing with Quantum Dots and an Image Sensor for Image Classification," IEEE International Conference on Rebooting Computing (ICRC), December 2024.
[6] Y. Gomi, K. Takami, R. Mizuno, M. Niikura, Y. Deng, S. Kawase, Y. Watanabe, S. Abe, W. Liao, M. Tampo, I. Umegaki, S. Takeshita, K. Shimomura, Y. Miyake, and M. Hashimoto, "Muon-Induced SEU Cross Sections of 12-nm FinFET and 28-nm Planar SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2023.
[7] M. Yoshida, R. Iwamoto, M. Itoh, and M. Hashimoto, "Stuck Errors in Bits and Blocks in GDDR6 under High-Energy Neutron Irradiation," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2023.
[8] R. Iwamoto and M. Hashimoto, "Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication," Proceedings of International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2023. [pdf]
[9] K. Takami, Y. Gomi, S. Abe, W. Liao, S. Manabe, T. Matsumoto, and M. Hashimoto, "Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons," Proceedings of International Reliability Physics Symposium (IRPS), March 2023. [pdf]
[10] M. Harimaya, R. Shirai, and M. Hashimoto, "Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers," Proceedings of International Conference on Intelligent User Interfaces (IUI), March 2023. [pdf]
[11] R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, and I. Umegaki, "Study of Muon Capture Reaction on Si Via In-Beam Muon Activation," Topical Workshops on Modern Aspects of Nuclear Structure, February 2023.
[12] S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, and Y. Watanabe, "A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.
[13] K. Ito, H. Itsuji, T. Uezono, T. Toba, M. Itoh, and M. Hashimoto, "Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.
[14] M. Kamibayashi, K. Kobayashi, and M. Hashimoto, "Single Bit Upsets Versus Burst Errors of Stacked-Capacitor DRAMs Induced by High-Energy Neutron -SECDED Is No Longer Effective-," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2022.
[15] M. Hashimoto, Y. Zhang, and K. Ito, "Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards," Proceedings of International Conference on Solid State Devices and Materials (SSDM), September 2022.
[16] T. Tanaka, R. Shirai, and M. Hashimoto, "DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2022. [pdf]
[17] M. Tanaka, J. Yu, M. Nakagawa, N. Tate, and M. Hashimoto, "Investigating Small Device Implementation of FRET-Based Optical Reservoir Computing," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2022. [pdf]
[18] D. Fujimoto, Y. Kim, Y. Hayashi, N. Homma, M. Hashimoto, T. Sato, and J.-L. Danger, "SASIMI: Evaluation Board for EM Information Leakage from Large Scale Cryptographic Circuits," IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity, August 2022. [pdf]
[19] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections," Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 60-63, March 2022. [pdf]
[20] R. Shirai and M. Hashimoto, "Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart Leds," Proceedings of International Conference on Intelligent User Interfaces (IUI), 89–92, March 2022. [pdf]
[21] R. Shirai and M. Hashimoto, "Submarine LED: Wirelessly Powered Underwater Display Controlling Its Buoyancy," Proceedings of SIGGRAPH Asia, December 2021. [pdf]
[22] A. Lopez, M. Hashimoto, M. Motomura, and J. Yu, "Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks," Proceedings of British Machine Vision Conference (BMVC), November 2021. [pdf]
[23] T. Hsu, D. Yang, W. Liao, M. Itoh, M. Hashimoto, , and J. Liou, "Processor SER Estimation with ACE Bit Analysis," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2021.
[24] T. Cheng and M. Hashimoto, "Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. [pdf]
[25] T. Tanaka, M. Hashimoto, and Y. Takeuchi, "Linear Programming Based Reliable Software Performance Model Construction with Noisy CPU Performance Counter Values," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), March 2021.
[26] M. Hashimoto and J. Chen, "Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2021. [pdf]
[27] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]
[28] D. Liang, M. Hashimoto, and H. Awano, "BloomCA: a Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]
[29] T. Imagawa, J. Yu, M. Hashimoto, and H. Ochi, "MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA," Proceedings of Design, Automation and Test in Europe Conference (DATE), February 2021. [pdf]
[30] T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 284 -- 290, January 2021. [pdf]
[31] T. Kato, M. Tampo, S. Takeshita, Y. Miyake, H Tanaka, and M. Hashimoto, "Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles," IEEE Nuclear and Space Radiation Effects Conference (NSREC), November 2020.
[32] J. Chen and M. Hashimoto, "Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction," Proceedings of International Test Conference (ITC), November 2020. [pdf]
[33] H. Itsuji, T. Uezono, T. Toba, K. Ito, and M. Hashimoto, "Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing," Proceedings of International Test Conference (ITC), November 2020. [pdf]
[34] A. Lopez, J. Yu, and M. Hashimoto, "Low-Cost Reservoir Computing Using Cellular Automata and Random Forests," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), October 2020. [pdf]
[35] Y. Zhang, K. Ito, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.
[36] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.
[37] K. Onishi, J. Yu, and M. Hashimoto, "Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network," Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS), August 2020. [pdf]
[38] R. Shimizu, R. Shirai, and M. Hashimoto, "Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), pages 57--60, August 2020. [pdf]
[39] Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, "Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling," International Workshop on Logic and Synthesis (IWLS), July 2020.
[40] X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy," Technical Digest of VLSI Symposium on Technology, June 2020. [pdf]
[41] H. Awano and M. Hashimoto, "BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA," Proceedings of Design, Automation and Test in Europe Conference (DATE), April 2020. [pdf]
[42] R. Doi, X. Bai, T. Sakamoto, and M. Hashimoto, "Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA," Proceedings of Design, Automation and Test in Europe Conference (DATE), April 2020. [pdf]
[43] S. Abe, T. Sato, J. Kuroda, S. Manabe, Y. Watanabe, W. Liao, K. Ito, M. Hashimoto, M. Harada, K. Oikawa, and Y. Miyake, "Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets," Proceedings of International Symposium on Reliability Physics (IRPS), April 2020. [pdf]
[44] W. Liao, K. Ito, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2020. [pdf]
[45] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]
[46] Z. Yan, Y. Shi, W. Liao, M. Hashimoto, X. Zhou, and C. Zhuo, "When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020. [pdf]
[47] M. Hashimoto and W. Liao, "Soft Error and Its Countermeasures in Terrestrial Environment," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2020. [pdf]
[48] T. Tanio, J. Yu, and M. Hashimoto, "Training Data Reduction Using Support Vectors for Neural Networks," Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), November 2019. [pdf]
[49] S. Fukui, J. Yu, and M. Hashimoto, "Distilling Knowledge for Non-Neural Networks," Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC), November 2019. [pdf]
[50] S. Sombatsiri, J. Yu, M. Hashimoto, and Y. Takeuchi, "A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2019.
[51] T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, and A. Sato, "Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.
[52] K. Ito, W. Liao, M. Hashimoto, J. Kuroda, S. Manabe, Y. Watanabe, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.
[53] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Impact of Incident Angle on Negative Muon-Induced SEU Cross Section of 65-nm Bulk SRAM," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.
[54] J. Kuroda, S. Manabe, Y. Watanabe, K. Ito, W. Liao, M. Hashimoto, S. Abe, M. Harada, K. Oikawa, and Y. Miyake, "Measurement of Single-Event Upsets in 65-nm Bulk SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2019.
[55] T.-Y. Cheng, J. Yu, and M. Hashimoto, "Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier," Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), July 2019. [pdf]
[56] J. Nagayama, Y. Masuda, M. Takeshige, Y. Ogawa, M. Hashimoto, and Y. Momiyama, "Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP," Design Automation Conference, Designer/IP Track, June 2019.
[57] J. Chen and M. Hashimoto, "A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), June 2019. [pdf]
[58] H. Numata, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA," Proceedings of Silicon Nanoelectronics Workshop, June 2019. [pdf]
[59] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, S. Takeshita, and Y. Miyake, "Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2019. [pdf]
[60] P. Chen, R. Shirai, and M. Hashimoto, "Coverage-Scalable Instant Tabletop Positioning System with Self-Localizable Anchor Nodes," Proceedings of International Conference on Intelligent User Interfaces (IUI), March 2019. [pdf]
[61] R. Doi, J. Yu, and M. Hashimoto, "Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]
[62] Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto, "Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2018. [pdf]
[63] K. Mitsunari, J. Yu, and M. Hashimoto, "Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 55-58, November 2018. [pdf]
[64] M. Hashimoto, W. Liao, S. Manabe, and Y. Watanabe, "Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2018. [pdf]
[65] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, and S. Abe, "Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.
[66] W. Liao, M. Hashimoto, S. Manabe, S. Abe, and Y. Watanabe, "Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.
[67] S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, and Y. Watanabe, "Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2018.
[68] K. Itoh, J. Yu, and M. Hashimoto, "Adapting Soft Cascade to Mac Operations of Convolutional Neural Networks," Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC), August 2018.
[69] R. Doi and M. Hashimoto, "SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]
[70] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018. [pdf]
[71] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018. [pdf]
[72] R. Shirai, T. Hirose, and M. Hashimoto, "A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes," Proceedings of International NEWCAS Conference, pages 152--156, June 2018. [pdf]
[73] J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, "An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency," Proceedings of IEEE Workshop on Signal and Power Integrity (SPI), May 2018. [pdf]
[74] T. Nakayama and M. Hashimoto, "Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature," Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2018. [pdf]
[75] K.-W. Lin, M. Hashimoto, and Y.-L. Li, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties," Proceedings of International Symposium on Quality Electronic Design (ISQED), March 2018. [pdf]
[76] M. Hashimoto and Y. Masuda, "MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)," Proceedings of China Semiconductor Technology International Conference (CSTIC), March 2018. [pdf]
[77] Y. Masuda and M. Hashimoto, "MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. [pdf]
[78] R. Shirai, T. Hirose, and M. Hashimoto, "Dedicated Antenna Less Power Efficient OOK Transmitter for mm-Cubic IoT Nodes," Proceedings of European Microwave Conference (EuMC), pages 101--104, October 2017. [pdf]
[79] W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2017.
[80] S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, "Momentum and Supply Voltage Dependencies of SEUs Induced by Low-Energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2017.
[81] M. Hashimoto, R. Shirai, Y. Itoh, and T. Hirose, "Toward Real-Time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)," Proceedings of IEEE International Conference on ASIC, pages 1087--1091, October 2017. [pdf]
[82] M. Hashimoto, W. Liao, and S. Hirokawa, "Soft Error Rate Estimation with TCAD and Machine Learning (Invited)," Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2017. [pdf]
[83] K.-W. Lin, Y.-L. Li, and M. Hashimoto, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles," Proceedings of IEEE Intelligent Vehicles Symposium (IV), pages 1465--1470, June 2017. [pdf]
[84] W. Liao, S. Hirokawa, R. Harada, and M. Hashimoto, "Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V --," Proceedings of International NEWCAS Conference, pages 33-37, June 2017. [pdf]
[85] R. Shirai, J. Kono, T. Hirose, and M. Hashimoto, "Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in mm^3-Class Sensor Node," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pages 124--127, May 2017. [pdf]
[86] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices," Proceedings of IEEE Wireless Power Transfer Conference (WPTC), May 2017. [pdf]
[87] K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, and M. Hashimoto, "GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction," Proceedings of International Conference on Intelligent User Interfaces (IUI), pages 173--178, March 2017. [pdf]
[88] N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic," Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2016. [231.PDF]
[89] Y. Masuda, M. Hashimoto, and T. Onoye, "Critical Path Isolation for Time-To-Failure Extension and Lower Voltage Operation," Proceedings of International Conference on Computer-Aided Design (ICCAD), November 2016. [230.pdf]
[90] Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, and M. Hashimoto, "Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [232.pdf]
[91] S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, and M. Hashimoto, "Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes," Proceedings of International Symposium on Antennas and Propagation (ISAP), October 2016. [pdf]
[92] H.-Y. Su, B.-S. Wang, S.-Y. Hsieh, Y.-L. Li, I-H. Wu, C.-C. Wu, W.-C. Shih, H. Onodera, and M. Hashimoto, "Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), October 2016.
[93] S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, and M. Hashimoto, "Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2016. [pdf]
[94] H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, and T. Sugibayashi, "Novel Processor Architecture for Onboard Infrared Sensors (Invited)," Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV, volume 9973, August 2016.
[95] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2016. [pdf]
[96] Y. Masuda, M. Hashimoto, and T. Onoye, "Hardware-Simulation Correlation of Timing Error Detection Performance of Software-Based Error Detection Mechanisms," Proceedings of International On-Line Testing Symposium (IOLTS), pages 84--89, July 2016. [228.pdf]
[97] C.-C. Hsu, M. P.-H. Lin, and M. Hashimoto, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Proceedings of System Level Interconnect Prediction (SLIP) Workshop, June 2016. [229.pdf]
[98] Y. Masuda, M. Hashimoto, and T. Onoye, "Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[99] R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2016.
[100] U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, and B. Li, "Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited)," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 705--711, January 2016. [227.pdf]
[101] N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-Outs," Technical Digest of IEEE International Electron Devices Meeting (IEDM), pages 32--35, December 2015. [225.PDF]
[102] Y. Masuda, M. Hashimoto, and T. Onoye, "Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise," Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 315-322, November 2015. [224.pdf]
[103] R. Doi, M. Hashimoto, and T. Onoye, "An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication," Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), November 2015.
[104] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," Proceedings of International Test Conference (ITC), October 2015. [223.pdf]
[105] Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, and M. Hashimoto, "A Wireless Power Transfer System for Small-Sized Sensor Applications," Proceedings of International Conference on Solid State Devices and Materials (SSDM), pages 154--155, September 2015.
[106] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.
[107] M. Ueno, M. Hashimoto, and T. Onoye, "Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization," Proceedings of International On-Line Testing Symposium (IOLTS), pages 188--193, July 2015. [222.pdf]
[108] M. Hashimoto, "Run-Time Performance Adaptation: Opportunities and Challenges (Invited)," Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), June 2015. [226.pdf]
[109] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [215.pdf]
[110] T. Uemura and M. Hashimoto, "Investigation of Single Event Upset and Total Ionizing Dose in FeRAM for Medical Electronic Tag," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [216.pdf]
[111] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]
[112] S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, "3D Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method," Proceedings of Virtual Reality Conference (VR), March 2015. [218.pdf]
[113] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 731--736, January 2015. [214.pdf]
[114] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015. [213.pdf]
[115] T. Amaki, M. Hashimoto, and T. Onoye, "An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 4--5, January 2015. [212.pdf]
[116] M. Hashimoto, "Stochastic Verification of Run-Time Performance Adaptation with Field Delay Testing (Invited)," Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS), pages 751--754, November 2014. [207.pdf]
[117] M. Hashimoto, "Opportunities and Verification Challenges of Run-Time Performance Adaptation (Invited)," Proceedings of Asian Test Symposium (ATS), pages 248--253, November 2014. [206.pdf]
[118] M. Hashimoto, "Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited)," Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2014. [205.pdf]
[119] A. Iokibe, M. Hashimoto, and T. Onoye, "Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground," Proceedings of International Conference on Sensing Technology (ICST), pages 188--193, September 2014. [204.pdf]
[120] T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, "Optimizing Well-Configuration for Minimizing Single Event Latchup," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[121] R. Harada, S. Hirokawa, and M. Hashimoto, "Measurement of Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4 V SRAMs," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[122] T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, "Preventing Single Event Latchup with Deep P-Well on P-Substrate," Proceedings of International Reliability Physics Symposium (IRPS), June 2014. [203.pdf]
[123] M. Ueno, M. Hashimoto, and T. Onoye, "Trace-Based Fault Localization with Supply Voltage Sensor," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 77--81, March 2014.
[124] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, and T. Onoye, "Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2013. [199.pdf]
[125] S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, "Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing," Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 107--114, November 2013. [193.PDF]
[126] J. Kono, M. Hashimoto, and T. Onoye, "Feasibility Evaluation of Near-Field Communication in Clay with 1-mm^3 Antenna," Proceedings of Asia-Pacific Microwave Conference (APMC), pages 1121--1123, November 2013. [194.pdf]
[127] T. Amaki, M. Hashimoto, and T. Onoye, "A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 133--136, November 2013. [195.pdf]
[128] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313--316, November 2013. [196.pdf]
[129] R. Harada, M. Hashimoto, and T. Onoye, "NBTI Characterization Using Pulse-Width Modulation," IEEE/ACM Workshop on Variability Modeling and Characterization, November 2013.
[130] M. Hashimoto, "Soft Error Immunity of Subthreshold SRAM (Invited)," Proceedings of IEEE International Conference on ASIC, pages 91--94, October 2013. [192.pdf]
[131] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[132] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[133] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[134] T. Shinada, M. Hashimoto, and T. Onoye, "Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes," Proceedings of International NEWCAS Conference, June 2013. [188.pdf]
[135] M. Ueno, M. Hashimoto, and T. Onoye, "Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures," Proceedings of Reconfigurable Architectures Workshop (RAW), pages 301--305, May 2013. [187.pdf]
[136] Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, and S. Nassif, "Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator," Proceedings of IEEE European Test Symposium (ETS), pages 106--111, May 2013. [186.pdf]
[137] M. Hashimoto, "Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited)," China Semiconductor Technology International Conference (CSTIC), pages 1079--1084, March 2013. [183.pdf]
[138] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012. [174.pdf]
[139] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Converter Based on MINIMAX Sampling," Proceedings of International SoC Design Conference (ISOCC), 120 -- 123, November 2012. [176.pdf]
[140] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of NBTI-­Induced Pulse-Width Modulation on SET Pulse-Width Measurement," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.
[141] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2012. [170.pdf]
[142] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2012.
[143] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "SET Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects," Proceedings of International Reliability Physics Symposium (IRPS), April 2012. [168.PDF]
[144] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 283--289, February 2012. [167.pdf]
[145] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 189--194, September 2011. [162.pdf]
[146] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011. [163.pdf]
[147] T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "NBTI Mitigation by Giving Random Scan-In Vectors During Standby Mode," Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pages 152--161, September 2011.
[148] M. Hashimoto and H. Fuketa, " Adaptive Performance Compensation with On-Chip Variation Monitoring (Invited)," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011. [160.pdf]
[149] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on MINIMAX Sampling," Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011. [161.pdf]
[150] T. Amaki, M. Hashimoto, and T. Onoye, "An Oscillator-Based True Random Number Generator with Jitter Amplifier," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pages 725--728, May 2011. [157.pdf]
[151] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing," Proceedings of International Reliability Physics Symposium (IRPS), pages 253--257, April 2011. [156.PDF]
[152] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 46--51, April 2011.
[153] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with RO-Based Sensors," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 13--18, March 2011.
[154] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), March 2011.
[155] K. Shinkai and M. Hashimoto, "Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 683--688, January 2011. [152.pdf]
[156] T. Amaki, M. Hashimoto, and T. Onoye, "Jitter Amplifier for Oscillator-Based True Random Number Generator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 81--82, January 2011. [153.pdf]
[157] M. Hashimoto, "Run-Time Adaptive Performance Compensation Using On-Chip Sensors (Invited)," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 285--290, January 2011. [154.pdf]
[158] Y. Takai, M. Hashimoto, and T. Onoye, "Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation," Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pages 213--216, October 2010. [146.pdf]
[159] T. Okumura and M. Hashimoto, "Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2010. [147.pdf]
[160] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling," Proceedings of International Workshop on Information Security Applications (WISA), pages 107-121, August 2010.
[161] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010. [140.PDF]
[162] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," ACM Great Lake Symposium on VLSI (GLSVLSI), pages 197--202, May 2010. [143.pdf]
[163] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO," Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010. [139.pdf]
[164] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation," Proceedings of IEEE COOL Chips, page 190, April 2010. [145.pdf]
[165] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 646--651, March 2010. [137.pdf]
[166] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 839--844, March 2010. [138.pdf]
[167] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 41--46, March 2010.
[168] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 89--94, March 2010.
[169] T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, "Gate Delay Estimation in STA under Dynamic Power Supply Noise," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 775 -- 780, January 2010. [132.pdf]
[170] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), 361 -- 362, January 2010. [131.pdf]
[171] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient VLSI Architecture for Signal Processing," Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009. [142.pdf]
[172] S. Ninomiya and M. Hashimoto, "Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving SSTA Accuracy," Proceedings of IEEE International SOC Conference (SOCC), pages 337--340, September 2009. [141.pdf]
[173] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 215--218, September 2009. [127.pdf]
[174] K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 51--56, August 2009. [125.pdf]
[175] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009. [133.pdf]
[176] S. Watanabe, M. Hashimoto, and T. Sato, "A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 401--407, March 2009. [122.pdf]
[177] Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 236--241, March 2009.
[178] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[179] K. Shinkai and M. Hashimoto, "A Gate Delay Model Over Wide-Range of Process and Environmental Variability," ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 79--84, February 2009.
[180] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009. [115.pdf]
[181] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 266-271, January 2009. [116.pdf]
[182] T. Enami, M. Hashimoto, and T. Sato, "Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis," Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 420--425, November 2008. [110.pdf]
[183] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 397--400, November 2008. [109.pdf]
[184] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," Proceedings of Workshop on Test Structure Design for Variability Characterization, November 2008.
[185] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008. [123.pdf]
[186] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 3--8, August 2008. [106.pdf]
[187] S. Watanabe, M. Hashimoto, and T. Sato, "Cascading Dependent Operations for Mitigating Timing Variability," Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008. [105.pdf]
[188] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays," In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.
[189] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --," Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI), pages 387--390, May 2008. [104.pdf]
[190] T. Enami, S. Ninomiya, and M. Hashimoto, "Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise," Proceedings of ACM International Symposium on Physical Design (ISPD), pages 160-167, April 2008. [107.pdf]
[191] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 520--525, March 2008. [102.PDF]
[192] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 107--108, January 2008. [97.pdf]
[193] L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, "High Performance Current-Mode Differential Logic," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 720--725, January 2008. [98.pdf]
[194] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed," Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 233-237, October 2007.
[195] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," Proceedings of 37th European Solid-State Device Research Conference (ESSDERC), pages 115--118, September 2007. [92.pdf]
[196] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 783--786, September 2007. [90.pdf]
[197] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and Chung-Kuan Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 869--872, September 2007. [91.pdf]
[198] K. Shinkai, M. Hashimoto, and T. Onoye, "Future Prediction of Self-Heating in Short Intra-Block Wires," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 660-665, March 2007. [82.PDF]
[199] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 47-53, November 2006. [22.pdf]
[200] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects," In Proceedings of IEEE International Conference on Computer Design (ICCD), pages 70-75, October 2006. [23.pdf]
[201] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 721-724, September 2006. [24.pdf]
[202] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC),, pages 861-864, September 2006. [25.pdf]
[203] T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of LCD Driver Circuit for Technology Migration," In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), volume 1, I25-I28, July 2006. [28.pdf]
[204] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006. [65.pdf]
[205] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations," In ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 59-64, February 2006.
[206] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006. [30.pdf]
[207] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction," In Proceedings of International Workshop on Compact Modeling (IWCM), pages 51-56, January 2006.
[208] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design for Liquid Crystal Displays," In Proceedings of IEEE International Region 10 Conference, number 1C-03.3, November 2005. [64.pdf]
[209] T. Kouno, M. Hashimoto, and H. Onodera, "Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 453-456, November 2005. [52.pdf]
[210] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip High-Throughput Global Signaling," In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 79-82, October 2005. [50.pdf]
[211] S. Uemura, T. Miyazaki, M. Hashimoto, and H. Onodera, "Estimation of Maximum Oscillation Frequency for CMOS LCVCOs," In Proceedings of IEEJ International Analog VLSI Workshop, October 2005.
[212] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Delay Variation Due to Inductive Coupling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 305-308, September 2005. [26.pdf]
[213] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 613-616, September 2005. [27.pdf]
[214] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix LCD," In Proceedings of European Conference on Circuit Theory and Design, number 3e-212, August 2005. [54.pdf]
[215] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 201-202, May 2005. [49.pdf]
[216] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pages 160-163, April 2005. [29.pdf]
[217] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics," In Proceedings of International Meeting for Future of Electron Devices, Kansai, pages 33-34, April 2005.
[218] A. Muramatsu, M. Hashimoto, and H. Onodera, "Effects of On-Chip Inductance on Power Distribution Grid," In Proceedings of International Symposium on Physical Design (ISPD), pages 63-69, April 2005. [46.pdf]
[219] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-Tree Structure," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 402-407, March 2005. [51.PDF]
[220] T. Sato, M. Hashimoto, and H. Onodera, "Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 723-728, January 2005. [31.pdf]
[221] M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, "Timing Analysis Considering Temporal Supply Voltage Fluctuation," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1098-1101, January 2005. [32.pdf]
[222] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop RL Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005. [33.pdf]
[223] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005. [34.pdf]
[224] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), D9-D10, January 2005. [35.pdf]
[225] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip Global Signaling," In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pages 87-100, November 2004.
[226] M. Hashimoto, J. Yamaguchi, and H. Onodera, "Timing Analysis Considering Spatial Power/Ground Level Variation," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 814-820, November 2004. [41.pdf]
[227] M. Hashimoto, A. Tsuchiya, and H. Onodera, "On-Chip Global Signaling by Wave Pipelining," In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 311-314, October 2004. [56.pdf]
[228] A. Muramatsu, M. Hashimoto, and H. Onodera, "LSI Power Network Analysis with On-Chip Wire Inductance," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 55-60, October 2004.
[229] T. Sato, M. Hashimoto, and H. Onodera, "An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 66-72, October 2004.
[230] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 214-219, October 2004.
[231] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL," In IEEJ International Analog VLSI Workshop, pages 45-50, October 2004.
[232] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 489-492, September 2004. [66.pdf]
[233] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of CMOS Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pages 434-435, August 2004. [55.pdf]
[234] M. Hashimoto, K. Fujimori, and H. Onodera, "Automatic Generation of Standard Cell Library in VDSM Technologies," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 36-41, March 2004. [53.PDF]
[235] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 691-696, January 2004. [37.pdf]
[236] T. Miyazaki, M. Hashimoto, and H. Onodera, "A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 545-546, January 2004. [36.pdf]
[237] M. Hashimoto, Y. Yamada, and H. Onodera, "Equivalent Waveform Propagation for Static Timing Analysis," In Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pages 169-175, November 2003. [42.pdf]
[238] M. Hashimoto, Y. Yamada, and H. Onodera, "Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 18-23, April 2003. [45.pdf]
[239] Y. Yamada, M. Hashimoto, and H. Onodera, "Slew Calculation Against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 280-287, April 2003.
[240] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Frequency Determination for Interconnect RLC Extraction," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 288-293, April 2003.
[241] T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, and M. Hashimoto, "Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 149-155, January 2003. [40.pdf]
[242] M. Hashimoto, K. Fujimori, and H. Onodera, "Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 589-590, January 2003. [38.pdf]
[243] M. Hashimoto, D. Hiramatsu, A. Tsuchiya, and H. Onodera, "Interconnect Structures for High-Speed Long-Distance Signal Transmission," In Proceedings of IEEE International ASIC/SOC Conference, pages 426-430, September 2002. [57.pdf]
[244] M. Hashimoto, Y. Hayashi, and H. Onodera, "Experimental Study on Cell-Base High-Performance Datapath Design," In Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS), pages 283-287, June 2002.
[245] M. Hashimoto, M. Takahashi, and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," In Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD), pages 126-130, April 2002. [43.pdf]
[246] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 377-381, October 2001.
[247] M. Takahashi, M. Hashimoto, and H. Onodera, "Crosstalk Noise Estimation for Generic RC Trees," In Proceedings of International Conference on Computer Design (ICCD), pages 110-116, September 2001. [58.pdf]
[248] H. Onodera, M. Hashimoto, and T. Hashimoto, "ASIC Design Methodology with On-Demand Library Generation," In Proceedings of Symposium on VLSI Circuits, pages 57-60, June 2001. [59.pdf]
[249] M. Hashimoto and H. Onodera, "Increase in Delay Uncertainty by Performance Optimization," In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), volume V, pages 379-382, May 2001. [60.pdf]
[250] M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 359-365, January 2001. [39.pdf]
[251] M. Hashimoto and H. Onodera, "A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing," In Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 34-37, December 2000.
[252] T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, and H. Onodera, "Vector Quantization Processor for Mobile Video Communication," In Proceedings of IEEE International ASIC/SOC Conference, pages 75-79, September 2000. [61.pdf]
[253] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Sizing Using Statistical Static Timing Analysis," In Proceedings of ACM International Symposium on Physical Design (ISPD), pages 111-116, April 2000. [44.pdf]
[254] M. Hashimoto and H. Onodera, "A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis," In Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 115-121, April 2000.
[255] M. Hashimoto, H. Onodera, and K. Tamaru, "Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design," In Proceedings of the 36th IEEE/ACM Design Automation Conference (DAC), pages 446-451, June 1999. [47.pdf]
[256] M. Hashimoto, H. Onodera, and K. Tamaru, "A Power Optimization Method Considering Glitch Reduction by Gate Sizing," In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 221-226, August 1998. [48.pdf]
[257] M. Hashimoto, H. Onodera, and K. Tamaru, "Input Reordering for Power and Delay Optimization," In Proceedings of IEEE International ASIC Conference and Exhibit, pages 194-198, September 1997. [62.pdf]
国内会議(査読付き)
[1] 岩本陸, 橋本昌宜, "GPU アプリケーションのスレッド間通信を用いた不正メモリアクセス検出手法の検討," 情報処理学会DAシンポジウム, 2022年8月.
[2] 田上凱斗, 橋本昌宜, "RISC-Vプロセッサにおける故障注入実験及び中性子照射実験の結果比較," 情報処理学会DAシンポジウム, 2022年8月.
[3] Y. Sun, R. Doi, and M. Hashimoto, "Rc Extraction-Free Wiring Delay Analysis Focusing on Number of On-State Switches for Via-Switch Fpga," 情報処理学会DAシンポジウム, August 2019.
[4] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測," 第19回 回路とシステム(軽井沢)ワークショップ, pages 5-10, 2006年4月. [73.pdf]
[5] 新開健一, 橋本昌宜, 黒川敦, 尾上孝雄, "電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル," 第19回 回路とシステム(軽井沢)ワークショップ, pages 559-564, 2006年4月. [75.pdf]
[6] 小林宏行, 小野信任, 佐藤高史, 岩井二郎, 橋本昌宜, "統計的STAの有効性の検証手法," 第19回 回路とシステム(軽井沢)ワークショップ, pages 553-558, 2006年4月. [74.pdf]
[7] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線の伝達特性ノ基づく抽出周波数決定手法," 情報処理学会DAシンポジウム, pages 169-174, 2005年8月.
[8] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送における終端抵抗決定手法," 第18回 回路とシステム(軽井沢)ワークショップ, pages 425-430, 2005年4月.
[9] 村松篤, 橋本昌宜, 小野寺秀俊, "オンチップインダクタンスを考慮したLSI電源配線網解析," 情報処理学会DAシンポジウム, pages 277-282, 2004年7月.
[10] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線RL抽出におけるリターンパス選択手法," 情報処理学会DAシンポジウム, pages 175-180, 2004年7月.
[11] 佐藤高史, 市宮淳次, 小野信任, 蜂屋孝太郎, 橋本昌宜, "フロアプランにおけるオンチップ熱ばらつきの解析と対策," 情報処理学会DAシンポジウム, pages 133-138, 2004年7月.
[12] 金本俊幾, 阿久津滋聖, 中林太美世, 一宮敬弘, 蜂屋孝太郎, 石川博, 室本栄, 小林宏行, 橋本昌宜, 黒川敦, "遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価," 情報処理学会DAシンポジウム, pages 265-270, 2004年7月.
[13] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---," 第17回 回路とシステム(軽井沢)ワークショップ, pages 567-572, 2004年4月.
[14] 土谷亮, 橋本昌宜, 小野寺秀俊, "直交配線を持つオンチップ伝送線路の特性評価," 情報処理学会DAシンポジウム, pages 133-138, 2003年7月.
[15] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線R(f)L(f)C抽出のための代表周波数決定手法," 第16回 回路とシステム(軽井沢)ワークショップ, pages 61-66, 2003年4月.
[16] 林宙輝, 橋本昌宜, 小野寺秀俊, "セルベース設計環境を用いた高性能データパス設計法の検討," 情報処理学会DAシンポジウム, pages 113-118, 2002年7月.
[17] 金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法," 情報処理学会DAシンポジウム, pages 149-154, 2002年7月.
[18] 山口隼司, 橋本昌宜, 小野寺秀俊, "IRドロップを考慮した電源線構造の最適化手法," 情報処理学会DAシンポジウム, pages 253-258, 2002年7月.
[19] 平松大輔, 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速信号伝送を可能にするVLSI配線構造の検討," 情報処理学会DAシンポジウム, pages 155-160, 2002年7月.
[20] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスが配線遅延に及ぼす影響の定量的評価方法," 第15回 回路とシステム(軽井沢)ワークショップ, pages 493-498, 2002年4月.
[21] 高橋正郎, 橋本昌宜, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズ見積もり手法," 情報処理学会DAシンポジウム, pages 19-24, 2001年7月.
[22] 橋本昌宜, 小野寺秀俊, "セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 185-190, 2000年7月.
[23] 橋本昌宜, 小野寺秀俊, "静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法," 第13回 回路とシステム(軽井沢)ワークショップ, pages 137-142, 2000年4月.
[24] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 269-274, 1998年7月.
[25] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "入力端子接続最適化による消費電力削減手法," 情報処理学会DAシンポジウム, pages 99-104, 1997年7月.
研究会・全国大会等
[1] 橋本昌宜, 吉田正和, "GDDR6における高エネルギー中性子照射によるスタックビット・ブロックの発生," 宇宙科学技術連合講演会, 2023年10月.
[2] 松元拓人, 橋本昌宜, "量子ドットとイメージセンサを用いたリザバーコンピューティングによる画像分類," 電子情報通信学会ソサイエティ大会, 2023年9月.
[3] 五味唯美, 橋本昌宜, "ミューオン起因ソフトエラーの物理現象解明に向けた照射実験と解析," LSIとシステムのワークショップ, 2023年5月.
[4] 五味唯美, 高見一総, 水野るり惠, 新倉潤, Yifan DENG, 川瀬頒一郎, 渡辺幸信, 安部晋一郎, 廖望, 反保元伸, 梅垣いづみ, 竹下聡史, 下村浩一郎, 三宅康博, 橋本昌宜, "12-nm FinFETおよび28-nm プレナー型SRAMのミューオン起因ソフトエラー断面積の評価," 電子情報通信学会 集積回路研究会, 2023年4月.
[5] 上林幹宜, 小林和淑, 橋本昌宜, "LPDDR4 SDRAMとGDDR5 SDRAMのソフトエラー耐性の実測評価," 電子情報通信学会 VLSI設計技術研究会, 2023年1月.
[6] 橋本昌宜, "ミュオン起因ソフトエラーの測定と課題," 日本原子力学会2022年秋の大会, 2022年9月.
[7] 稲毛康太, 橋本昌宜, "モデル抽出攻撃に対して決定木構造漏洩がもたらす危険性評価," 電子情報通信学会総合大会講演論文集, 2022年3月.
[8] 田中雅文, 橋本昌宜, "FRETを利用したリザバーコンピューティングの小型デバイス実装の検討," 電子情報通信学会総合大会講演論文集, 2022年3月.
[9] 田中知成, 廖望, 橋本昌宜, 密山幸男, "仮想環境を用いたSRAM型FPGAにおける ソフトエラー評価手法," 情報処理学会SLDM研究会, 2022年3月.
[10] 根尾優一郎, 橋本昌宜, "CNNの組み合わせ回路実装に向けた重み調整によるLUT数削減手法の検討," 情報処理学会SLDM研究会, 2022年1月.
[11] 木村侑希大, 白井僚, 橋本昌宜, "小体積IoTノード向け磁界式バックスキャッタ通信手法の提案と評価," 電子情報通信学会 集積回路研究会, 2021年12月.
[12] 田中稔久, 白井僚, 橋本昌宜, "磁性体金属異物に対してロバストな直流磁界を用いた位置推定手法の検討," 電子情報通信学会 集積回路研究会, 2021年12月.
[13] 白井僚, 森聖太, 渡辺悠介, 中村柚希, 橋本昌宜, "360度視野角を有する3Dディスプレイの実現に向けた,極小画素ドットへの水中無線給電技術," 電子情報通信学会 集積回路研究会, 2021年12月.
[14] T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, "Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization," 電子情報通信学会 VLSI設計技術研究会, March 2021.
[15] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch," Work in Progress Session, Design Automation Conference (DAC), June 2016.
[16] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," 電子情報通信学会 VLSI設計技術研究会, March 2015.
[17] M. Hashimoto, M. Ueno, and T. Onoye, "Real-Time Supply Voltage Sensor for Trace-Based Fault Localization," Poster Session, International Test Conference (ITC), October 2014.
[18] M. Hashimoto, "Reliability Challenge for Exa-Scale Near-Threshold Computing -- Soft Error Perspective --," Elevator Talk Session, International Test Conference (ITC), September 2013.
[19] M. Hashimoto, "Adaptive Speed Control and Its Extremely-Low Error Rate Estimation," Elevator Talk Session, International Test Conference (ITC), November 2012.
[20] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on Minimax," 電子情報通信学会 集積回路研究会, number ICD2011-121, pages 105--107, December 2011.
[21] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史、尾上孝雄, "電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現," 電子情報通信学会 集積回路研究会,, number ICD2006-174, 2007年1月.
[22] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測," 電子情報通信学会 集積回路研究会, number ICD2006-173, 2007年1月.
[23] Jangsombatsiri Siriporn, 橋本昌宜, 尾上孝雄, "シャントコンダクタンスを挿入したオンチップ伝送線路特性評価," 第十回シリコンアナログRF研究会, 2006年11月.
[24] 小笠原泰弘, 新開健一, 榎並孝司, 阿部慎也, 二宮進有, 橋本昌宜, "ナノメートル世代のVLSIタイミング設計技術の研究," 第10回システムLSIワークショップ, pages 195-198, 2006年11月.
[25] 新開健一, 橋本昌宜, 尾上孝雄, "短距離ブロック内配線の自己発熱問題の将来予測," 2006年電子情報通信学会ソサイエティ大会講演論文集, number A-3-14, 2006年9月. [72.pdf]
[26] 伊地知孝仁, 橋本昌宜,高橋真吾,築山修治,白川功, "画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術," 電子情報通信学会 VLSI設計技術研究会, number VLD2005-131, 2006年3月.
[27] 上村晋一朗, 土谷亮, 橋本昌宜, 小野寺秀俊, "ロードマップに準拠したSPICEトランジスタモデルの構築," 2006年電子情報通信学会総合大会講演論文集, number A-3-16, 2006年3月. [76.pdf]
[28] 榎並孝司, 橋本昌宜, 尾上孝雄, "電源ノイズ解析のための回路動作部表現法の評価," 2006年電子情報通信学会総合大会講演論文集, number A-3-15, 2006年3月. [77.pdf]
[29] 土谷亮, 新名亮規, 橋本昌宜、小野寺秀俊, "CMLを用いたオンチップ長距離高速信号伝送技術の開発," 第9回システムLSIワークショップ, pages 275-278, 2005年11月.
[30] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり," 2005年電子情報通信学会ソサイエティ大会講演論文集, number C-12-39, 2005年9月. [79.pdf]
[31] 小笠原泰弘, 橋本昌宜, 尾上孝雄, "誘導性・容量性クロストークノイズによる遅延変動の測定と評価," 電子情報通信学会 集積回路研究会, number ICD2005-74, 2005年8月.
[32] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "SOIの基板抵抗率がLNAの性能に及ぼす影響の評価," 第四回シリコンアナログRF研究会, 2005年5月.
[33] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送用配線の解析的性能評価," 電子情報通信学会 VLSI設計技術研究会, number VLD2004-145, 2005年3月.
[34] 土谷亮, 橋本昌宜, 小野寺秀俊, "実測と電磁界解析による基板損失の評価," 第三回シリコンアナログRF研究会, 2005年1月.
[35] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "LC型VCO最大発振周波数の実験的検討," 第三回シリコンアナログRF研究会, 2005年1月.
[36] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶設計のための配線容量抽出手法," 電子情報通信学会 VLSI設計技術研究会(デザインガイア), number VLD2004-64, 2004年12月.
[37] 橋本昌宜, "ナノメートル世代のタイミング解析 -- 信号線・電源線ノイズ、ばらつき、熱への対応 --," 第8回システムLSIワークショップ, pages 191-200, 2004年11月.
[38] 内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, "システム液晶に適した配線間容量抽出の検討," 2004年電子情報通信学会ソサイエティ大会講演論文集, number A-1-16, 2004年9月.
[39] 橋本昌宜, 小野寺秀俊, "微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応--," 2004年電子情報通信学会ソサイエティ大会講演論文集, 2004年9月.
[40] 土谷亮, 橋本昌宜, 小野寺秀俊, "基板および周辺信号配線が配線特性に及ぼす影響の実測," 第二回シリコンアナログRF研究会, 2004年8月.
[41] 上村晋一朗, 橋本昌宜, 小野寺秀俊, "高周波CMOSデバイスモデルを用いたLCVCOの特性見積もりと実測," 第二回シリコンアナログRF研究会, 2004年8月.
[42] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響," 第一回シリコンアナログRF研究会, 2004年4月.
[43] 山口隼司, 橋本昌宜, 小野寺秀俊, "ゲート毎の電源電圧変動を考慮した静的遅延解析法," 電子情報通信学会 VLSI設計技術研究会, number ICD2003-236/VLD2003-143, 2004年3月.
[44] 村松篤, 橋本昌宜, 小野寺秀俊, "電源電圧変動に対するオンチップ配線インダクタンスの影響," 2004年電子情報通信学会総合大会講演論文集, number A-3-22, 2004年3月.
[45] 村松篤, 橋本昌宜, 小野寺秀俊, "電源配線の等価回路簡略化による電源解析高速化の検討," 平成15年度情報処理学会関西支部支部大会 VLSI研究会, number C-01, pages 169-172, 2003年11月.
[46] 宮崎崇仁, 橋本昌宜, 小野寺秀俊, "デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー," 電子情報通信学会集積回路研究会, number ICD2003-99, pages 29-34, 2003年9月.
[47] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号配線における波形歪みの影響," 2003年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 56, 2003年9月.
[48] 宮崎崇仁, 新名亮規, 橋本昌宜, 小野寺秀俊, "オンチップオシロ用サンプルホールド回路の広周波数帯域化," 2003年電子情報通信学会総合大会講演論文集, number C-12-34, page 103, 2003年3月.
[49] 土谷亮, 橋本昌宜, 小野寺秀俊, "信号配線と下層配線との結合に対する直交配線の影響," 2003年電子情報通信学会総合大会講演論文集, number A-3-14, page 81, 2003年3月.
[50] 村松篤, 橋本昌宜, 小野寺秀俊, "オンチップデカップリング容量の最適寄生抵抗値の決定法," 2003年電子情報通信学会総合大会講演論文集, number A-3-13, page 80, 2003年3月.
[51] 橋本昌宜, "LSI物理設計におけるSignal Integrity問題," 情報処理学会関西支部VLSIシステム研究会平成14年度第3回研究会, 2003年3月.
[52] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "静的遅延解析のための等価ゲート入力波形導出法 --VDSMプロセスに起因する波形歪みへの対応--," 情報処理学会システムLSI設計技術研究会, number 2003-SLDM-108-20, pages 111-116, 2003年1月.
[53] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "容量性クロストークを考慮した高精度タイミング解析に関する研究," 平成14年度情報処理学会関西支部支部大会 VLSI研究会, number C-3, pages 113-114, 2002年11月.
[54] 佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜, "インダクタンスに起因する配線遅延変動の統計的予測手法," 2002年電子情報通信学会ソサイエティ大会講演論文集, number TA-2-4, pages 247-248, 2002年9月.
[55] 橋本昌宜, "京大版スタンダードセルライブラリ," VDEC LSI デザイナーフォーラム 2002, 2002年9月.
[56] 藤森一憲, 橋本昌宜, 小野寺秀俊, "駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発," 電子情報通信学会VLSI設計技術研究会, number VLD2001-147/ICD2001-222, 2002年3月.
[57] 山田祐嗣, 橋本昌宜, 小野寺秀俊, "ゲート出力波形導出時の誤差要因とその影響の評価," 2002年電子情報通信学会総合大会講演論文集, number A-3-3, page 82, 2002年3月.
[58] 土谷亮, 橋本昌宜, 小野寺秀俊, "LSI配線インダクタンスに対する直交配線の影響," 2002年電子情報通信学会総合大会講演論文集, number A-3-23, page 102, 2002年3月.
[59] 橋本昌宜, 高橋正郎, 小野寺秀俊, "ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法," 情報処理学会システムLSI設計技術研究会(デザインガイア), number SLDM103-6, pages 39-44, 2001年11月.
[60] 高橋正郎, 橋本昌宜, 小野寺秀俊, "波形重ね合せによるクロストーク遅延変動量の見積もり手法," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-9, page 63, 2001年9月.
[61] 橋本昌宜, 高橋正郎, 小野寺秀俊, "ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-8, page 62, 2001年9月.
[62] 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速配線における RC モデルに基づく回路設計の限界," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 60, 2001年9月.
[63] 橋本昌宜, 高橋正郎, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用---," 2001年電子情報通信学会総合大会講演論文集, number A-3-6, page 84, 2001年3月.
[64] 高橋正郎, 橋本昌宜, 小野寺秀俊, "隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 ---," 2001年電子情報通信学会総合大会講演論文集, number A-3-5, page 83, 2001年3月.
[65] 橋本昌宜, 小野寺秀俊, "パスバランス回路における遅延不確かさの統計的解析," 電子情報通信学会VLSI設計技術研究会(デザインガイア), number VLD2000-72, 2000年11月.
[66] 橋本昌宜, 小野寺秀俊, "パスバランス回路における遅延不確かさの統計的解析," 2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-9, page 76, 2000年9月.
[67] 橋本昌宜, "オンデマンドライブラリを用いた最適LSI設計手法," VDEC LSI デザイナーフォーラム , 2000年8月.
[68] 橋本昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺秀俊, "オンデマンドライブラリを用いたシステムLSI詳細設計手法," 電子情報通信学会VLSI設計技術研究会, number VLD99-112/ICD99-269, 2000年3月.
[69] 橋本昌宜, 小野寺秀俊, "静的統計遅延解析を用いた最悪遅延時間計算手法," 2000年電子情報通信学会総合大会講演論文集, number A-3-13, page 81, 2000年3月.
[70] 橋本昌宜, 橋本鉄太郎,西川亮太,福田大輔,黒田慎介,菅俊介,神原弘之,小野寺秀俊, "オンデマンドライブラリを用いたシステムLSI詳細設計手法," 第3回 システムLSI琵琶湖ワークショップ, pages 279-281, 1999年11月.
[71] 橋本昌宜, 小野寺秀俊, "スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討," 1999年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-9, page 52, 1999年9月.
[72] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用---," 1998年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-5, 1998年9月.
[73] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "論理シミュレーションを用いた消費電力見積もりの高精度化手法," 1998年電子情報通信学会総合大会講演論文集, number A-3-5, page 91, 1998年3月.
[74] 橋本昌宜, 小野寺秀俊, 田丸啓吉, "入力端子接続最適化による遅延時間と消費電力の最適化手法," 1997年電子情報通信学会基礎・境界ソサイエティ大会講演論文集, number A-3-15, page 67, 1997年9月.
著書
[1] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, and T. Sakamoto, "Atomic Switch FPGA: Application for IoT Sensing Systems in Space," Book Chapter, Atomic Switch, Springer, March 2020.
[2] E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, and M. Sugihara, "Radiation-Induced Soft Errors," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.
[3] H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, and M. Tada, "Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.
[4] T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, and J. Yao, "Time-Dependent Degradation in Device Characteristics and Countermeasures by Design," Book chapter, VLSI Design and Test for Systems Dependability, Springer, August 2018.
[5] M. Hashimoto and R. Nair, Power Integrity for Nanoscale Integrated Systems, McGraw-Hill Professional,, 2014.
[6] M. Hashimoto and R. Nair, "Power Integrity Management in Integrated Circuits and Systems," Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR, May 2010.
[7] R. Nair, M. Hashimoto, and N. Srivastava, "IC Power Integrity and Optimal Power Delivery," Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR, May 2010.
解説
[1] 橋本昌宜, "環境放射線と半導体デバイスのソフトエラー ミューオン起因ソフトエラーの測定と課題," 日本原子力学会誌ATOMOΣ, volume 65, number 5, pages 323-325, 2023年5月.