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論文誌
[1] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]
[2] X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "Via-Switch FPGA: 65nm CMOS Implementation and Evaluation," IEEE Journal of Solid-State Circuits, volume 57, number 7, pages 2250-2262, July 2022. [pdf]
[3] R. Doi, X. Bai, T. Sakamoto, and M. Hashimoto, "A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 103-A, number 12, pages 1447--1455, December 2020. [pdf]
国際会議
[1] X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, "1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy," Technical Digest of VLSI Symposium on Technology, June 2020. [pdf]
[2] R. Doi, X. Bai, T. Sakamoto, and M. Hashimoto, "Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA," Proceedings of Design, Automation and Test in Europe Conference (DATE), April 2020. [pdf]
[3] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), pages 502--503, February 2020. [pdf]