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論文誌

[1] M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, "Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation," Japanese Journal of Applied Physics, volume 61, number SM0804, October 2022. [pdf]

[2] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2545--2553, December 2011. [166.pdf]