Detail of a work
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T. Cheng and M. Hashimoto, "Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling," Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. | |
ID | 566 |
分類 | 国際会議 |
タグ | adaptive bit-width dnn energy minimizing scaling training voltage |
表題 (title) |
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling |
表題 (英文) |
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著者名 (author) |
T. Cheng,M. Hashimoto |
英文著者名 (author) |
,M. Hashimoto |
キー (key) |
,M. Hashimoto |
定期刊行物名 (journal) |
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) |
定期刊行物名 (英文) |
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巻数 (volume) |
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号数 (number) |
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ページ範囲 (pages) |
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刊行月 (month) |
5 |
出版年 (year) |
2021 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id566, title = {Minimizing Energy of {DNN} Training with Adaptive Bit-Width and Voltage Scaling}, author = {T. Cheng and M. Hashimoto}, journal = {Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)}, month = {5}, year = {2021}, } |