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\documentclass{jarticle}
\usepackage{times}
\usepackage{fancyhdr}
\renewcommand{\baselinestretch}{0.85}
\setlength{\topmargin}{-10mm}
\setlength{\oddsidemargin}{0mm}
\setlength{\evensidemargin}{0mm}
\setlength{\textheight}{23.6cm}
\setlength{\textwidth}{16cm}
\title{\LARGE\bf 研究業績リスト}

\newcommand{\myName}{} %ここに名前が挿入される
\newcommand{\myAffiliation}{} %ここに所属が挿入される
\newcommand{\myTitle}{} %ここに肩書きが挿入される
\author{ \myAffiliation ~~ \myTitle  ~~ \myName }

\begin{document}
\maketitle

\pagestyle{fancy}
\thispagestyle{fancy}

\renewcommand{\headrulewidth}{0.5pt}
\renewcommand{\footrulewidth}{0.5pt}
\renewcommand{\sectionmark}[1]{\markright{#1}}
\fancyhf{}
\fancyhead[CE,CO]{\bf 研究業績リスト}
\fancyhead[RE,LO]{\bf \rightmark}
\fancyfoot[LE,RO]{\thepage}

\section{論文誌}
\label{sec:0}

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\begin{enumerate}
\item
Y. Masuda, T. Onoye, and M. Hashimoto, ``Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E100-A, number 7, pages 1452--1463, July 2017.
\item
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in {STA} under Dynamic Power  Supply Noise,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2447--2455, December 2010.
\item
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter  and Skew Due to Power Supply Noise and Process  Variation,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2399--2408, December 2010.
\item
T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 28, number 4, 541 - 553, April 2009.
\item
M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ``Timing Analysis Considering Temporal Supply Voltage Fluctuation,'' IEICE Trans. on Information and Systems, volume E91-D, number 3, pages 655--660, March 2008.
\item
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Transactions on Circuits and Systems II, volume 54, number 10, pages 868--872, October 2007.
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\section{国際会議}
\label{sec:1}

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\begin{enumerate}
\item
M. Hashimoto and J. Chen, ``Proactive Supply Noise Mitigation and Design Methodology for Robust {VLSI} Power Distribution (Invited),'' Proceedings of China Semiconductor Technology International Conference (CSTIC),   March 2021.
\item
J. Chen and M. Hashimoto, ``Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction,'' Proceedings of International Test Conference (ITC),   November 2020.
\item
R. Shirai, T. Hirose, and M. Hashimoto, ``A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes,'' Proceedings of International NEWCAS Conference,  pages 152--156, June 2018.
\item
J. Chen, T. Kanamoto, H. Kando, and M. Hashimoto, ``An On-Chip Load Model for Off-Chip {PDN} Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency,'' Proceedings of IEEE Workshop on Signal and Power Integrity (SPI),   May 2018.
\item
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, and Y. Miyake, ``Momentum and Supply Voltage Dependencies of {SEUs} Induced by Low-Energy Negative and Positive Muons in {65-nm} {UTBB-SOI} {SRAMs},'' Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS),   October 2017.
\item
Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to {SSO},'' Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI),  pages 19--20, May 2010.
\item
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, and M. Hashimoto, ``Gate Delay Estimation in {STA} under Dynamic Power Supply Noise,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC),  775 -- 780, January 2010.
\item
Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site {SoC} Power Integrity Verification,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC),  pages 107--108, January 2008.
\item
T. Sato, M. Hashimoto, and H. Onodera, ``An {IR-drop} Minimization by Optimizing Number and Location of Power Supply Pads,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI),  pages 66-72, October 2004.
\end{enumerate}
以上．
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