Detail of a work
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H. Awano and M. Hashimoto, "B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA," Integration, the VLSI Journal, 89, pp. 1-8, March 2023. | |
ID | 605 |
分類 | 論文誌 |
タグ | accelerator b2n2 bayesian bernoulli efficient fpga network neural resource sampler |
表題 (title) |
B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA |
表題 (英文) |
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著者名 (author) |
H. Awano,M. Hashimoto |
英文著者名 (author) |
,M. Hashimoto |
キー (key) |
,M. Hashimoto |
定期刊行物名 (journal) |
Integration, the VLSI Journal |
定期刊行物名 (英文) |
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巻数 (volume) |
89 |
号数 (number) |
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ページ範囲 (pages) |
1-8 |
刊行月 (month) |
3 |
出版年 (year) |
2023 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id605, title = {{B2N2:} Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on {FPGA}}, author = {H. Awano and M. Hashimoto}, journal = {Integration, the VLSI Journal}, volume = {89}, pages = {1-8}, month = {3}, year = {2023}, } |