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国際会議

[1] K. Suemitsu, K. Matsuoka, T. Sato, and M. Hashimoto, "Logic Locking Over TFHE for Securing User Data and Algorithms," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), January 2024. [pdf]

[2] H. Itsuji, T. Uezono, T. Toba, K. Ito, and M. Hashimoto, "Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing," Proceedings of International Test Conference (ITC), November 2020. [pdf]

[3] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018. [pdf]

[4] N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi, "50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic," Technical Digest of IEEE International Electron Devices Meeting (IEDM), December 2016. [231.PDF]

[5] A. Shinmyo, M. Hashimoto, and H. Onodera, "Design and Optimization of CMOS Current Mode Logic Dividers," In IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pages 434-435, August 2004. [55.pdf]