Table of works
Frequent tags in this search: mode:4 analysis:2 chip:1 cmos:1 considering:1 current:1 design:1 detection:1 dividers:1 during:1 fault:1 giving:1 gpus:1 interdependency:1 irradiation:1 load:1 logic:1 mitigation:1 model:1 multi-core:1 nbti:1 network-based:1 neural:1 neutron:1 object:1 operation:1 optimization:1 pdn:1 random:1 scan-in:1
4 publications are found. : URL for this page. : HTML
| Author (author) | Title (title) | Journal/Conference | Volume / Number | Pages (pages) | Published date | Impact factor / Acceptance | File | |
|---|---|---|---|---|---|---|---|---|
| Academic Journal |
J. Chen, H. Kando, T. Kanamoto, , M. Hashimoto |
A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions |
IEEE Transactions on Components, Packaging and Manufacturing Technology | 9(9) |
1669--1679 |
September 2019 |
pdf | |
| International Conference |
Y. Zhang, , , , , M. Hashimoto |
Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test |
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS) | October 2020 |
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| International Conference |
T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye |
NBTI Mitigation by Giving Random Scan-In Vectors During Standby Mode |
Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS) | 152--161 |
September 2011 |
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| International Conference |
A. Shinmyo, M. Hashimoto, H. Onodera |
Design and Optimization of CMOS Current Mode Logic Dividers |
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | 434-435 |
August 2004 |
55.pdf |