この検索内の頻出タグ: chip^:2 125^:1 55-nm^:1 analysis^:1 considering^:1 error^:1 errors^:1 event-wise^:1 every^:1 interdependency^:1 load^:1 measurement^:1 mode^:1 model^:1 multi-core^:1 ns^:1 operation^:1 pdn^:1 scanning^:1 soft^:1 sram^:1 transitions^:1 voltage-current-timing^:1

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論文誌

[1] Y. Gomi, A. Sato, W. Madany, K. Okada, S. Adachi, M. Itoh, and M.Hashimoto, "A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement," IEEE Solid-State Circuits Letters, volume 8, pages 245-248, September 2025. [pdf]

[2] J. Chen, H. Kando, T. Kanamoto, C. Zhuo, and M. Hashimoto, "A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions," IEEE Transactions on Components, Packaging and Manufacturing Technology, volume 9, number 9, pages 1669--1679, September 2019. [pdf]