Detail of a work
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Y. Gomi, A. Sato, W. Madany, K. Okada, S. Adachi, M. Itoh, and M.Hashimoto, "A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement," IEEE Solid-State Circuits Letters, 8, pp. 245-248, September 2025. | |
ID | 671 |
分類 | 論文誌 |
タグ | 125 55-nm chip error errors event-wise every measurement ns scanning soft sram |
表題 (title) |
A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement |
表題 (英文) |
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著者名 (author) |
Y. Gomi,A. Sato,W. Madany,K. Okada,S. Adachi,M. Itoh,M.Hashimoto |
英文著者名 (author) |
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キー (key) |
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定期刊行物名 (journal) |
IEEE Solid-State Circuits Letters |
定期刊行物名 (英文) |
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巻数 (volume) |
8 |
号数 (number) |
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ページ範囲 (pages) |
245-248 |
刊行月 (month) |
9 |
出版年 (year) |
2025 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id671, title = {A {55-nm} {SRAM} Chip Scanning Errors Every 125 {ns} for Event-Wise Soft Error Measurement}, author = {Y. Gomi and A. Sato and W. Madany and K. Okada and S. Adachi and M. Itoh and M.Hashimoto}, journal = {IEEE Solid-State Circuits Letters}, volume = {8}, pages = {245-248}, month = {9}, year = {2025}, } |