この検索内の頻出タグ: jitter^:3 dbc^:2 fsrms^:2 integrated^:2 128.4^:1 22^:1 292.2-to-321.4^:1 88.5^:1 analysis^:1 clock^:1 cmos^:1 compensation^:1 considering^:1 detector^:1 due^:1 generator^:1 ghz^:1 mmw^:1 nm^:1 noise^:1 phase/frequency^:1 pll^:1 power^:1 process^:1 reference^:1 ripple^:1 skew^:1 source^:1 spur^:1 spurious^:1

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論文誌

[1] W. Jin, Q. Cheng, Y. Liang, and M. Hashimoto, "An 88.5 fsrms Integrated Jitter and ‒76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector," IEEE Transactions on Circuits and Systems I: Regular Papers, 採録済. [pdf]

[2] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 Ghz Synchronized Source Generator with ‒58.7 Dbc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 Nm Cmos Technology," IEEE Transactions on Microwave Theory and Techniques, 採録済.

[3] T. Enami, K. Shinkai, S. Ninomiya, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2399--2408, December 2010. [148.pdf]