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W. Jin, Q. Cheng, Y. Liang, and M. Hashimoto, "An 88.5 fsrms Integrated Jitter and ‒76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector," IEEE Transactions on Circuits and Systems I: Regular Papers, 採録済.
ID 648
分類 論文誌
タグ 88.5 compensation dbc detector fsrms integrated jitter mmw phase/frequency pll reference ripple spur utilizing ‒76.2
表題 (title) An 88.5 fsrms Integrated Jitter and ‒76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector
表題 (英文)
著者名 (author) W. Jin,Q. Cheng,Y. Liang,M. Hashimoto
英文著者名 (author) ,,,M. Hashimoto
キー (key) ,,,M. Hashimoto
定期刊行物名 (journal) IEEE Transactions on Circuits and Systems I: Regular Papers
定期刊行物名 (英文)
巻数 (volume)
号数 (number)
ページ範囲 (pages)
刊行月 (month) 0
出版年 (year) (to appear)
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル pdf (application/pdf) [一般閲覧可]
BiBTeXエントリ
@article{id648,
         title = {An 88.5 {fsrms} Integrated Jitter and ‒76.2 {dBc} Reference Spur {mmW} {PLL} Utilizing a Ripple Compensation Phase/Frequency Detector},
        author = {W. Jin and Q. Cheng and Y. Liang and M. Hashimoto},
       journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
         month = {0},
          year = {(to appear)},
}