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6 件の該当がありました. : このページのURL : HTML


論文誌
[1] W. Liao, K. Ito, S. Abe, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 68, number 6, pages 1228-1234, June 2021. [pdf]
[2] T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, and A. Sato, "Irradiation Test of 65 nm Bulk SRAMs with DC Muon Beam at RCNP MuSIC Facility," IEEE Transactions on Nuclear Science, volume 67, number 7, 1555 -- 1559, July 2020. [pdf]
[3] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013. [197.pdf]
国際会議
[1] W. Liao, K. Ito, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2020. [pdf]
[2] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [215.pdf]
[3] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]