
- 論文誌
- [1] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 GHz Synchronized Source Generator with ‒58.7 dBc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 nm CMOS Technology," IEEE Transactions on Microwave Theory and Techniques, volume 73, number 10, pages 7572-7587, October 2025. [pdf]
- [2] W. Liao, K. Ito, S. Abe, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM," IEEE Transactions on Nuclear Science, volume 68, number 6, pages 1228-1234, June 2021. [pdf]
- [3] T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, and A. Sato, "Irradiation Test of 65 nm Bulk SRAMs with DC Muon Beam at RCNP MuSIC Facility," IEEE Transactions on Nuclear Science, volume 67, number 7, 1555 -- 1559, July 2020. [pdf]
- [4] T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, volume 60, number 6, pages 4362--4367, December 2013. [197.pdf]
- 国際会議
- [1] W. Liao, K. Ito, Y. Mitsuyama, and M. Hashimoto, "Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs," Proceedings of International Reliability Physics Symposium (IRPS), April 2020. [pdf]
- [2] T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, "Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM," Proceedings of International Symposium on Reliability Physics (IRPS), April 2015. [215.pdf]
- [3] T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, "Soft Error Immune Latch Design for 20 nm Bulk CMOS," Proceedings of International Reliability Physics Symposium (IRPS), April 2015. [217.pdf]