Detail of a work
| Tweet | |
| T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, "Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch," IEEE Transactions on Nuclear Science, 60(6), pp. 4362--4367, December 2013. | |
| ID | 368 |
| 分類 | 論文誌 |
| タグ | 28 mitigating multi-bit-latch multi-bit-upset nm well-slits |
| 表題 (title) |
Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch |
| 表題 (英文) |
|
| 著者名 (author) |
T. Uemura,T. Kato,H. Matsuyama,M. Hashimoto |
| 英文著者名 (author) |
T. Uemura,T. Kato,H. Matsuyama,M. Hashimoto |
| キー (key) |
T. Uemura,T. Kato,H. Matsuyama,M. Hashimoto |
| 定期刊行物名 (journal) |
IEEE Transactions on Nuclear Science |
| 定期刊行物名 (英文) |
|
| 巻数 (volume) |
60 |
| 号数 (number) |
6 |
| ページ範囲 (pages) |
4362--4367 |
| 刊行月 (month) |
12 |
| 出版年 (year) |
2013 |
| Impact Factor (JCR) |
|
| URL |
|
| 付加情報 (note) |
|
| 注釈 (annote) |
|
| 内容梗概 (abstract) |
|
| 論文電子ファイル | 197.pdf (application/pdf) [一般閲覧可] |
| BiBTeXエントリ |
@article{id368,
title = {Mitigating Multi-Bit-Upset with Well-Slits in 28 {nm} Multi-Bit-Latch},
author = {T. Uemura and T. Kato and H. Matsuyama and M. Hashimoto},
journal = {IEEE Transactions on Nuclear Science},
volume = {60},
number = {6},
pages = {4362--4367},
month = {12},
year = {2013},
}
|