Detail of a work
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K. Mitsunari, J. Yu, and M. Hashimoto, "Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features," Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 55-58, November 2018. | |
ID | 495 |
分類 | 国際会議 |
タグ | aggregated architecture channel detection fast features general hardware object |
表題 (title) |
Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features |
表題 (英文) |
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著者名 (author) |
K. Mitsunari,J. Yu,M. Hashimoto |
英文著者名 (author) |
K. Mitsunari,J. Yu,M. Hashimoto |
キー (key) |
K. Mitsunari,J. Yu,M. Hashimoto |
定期刊行物名 (journal) |
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC) |
定期刊行物名 (英文) |
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巻数 (volume) |
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号数 (number) |
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ページ範囲 (pages) |
55-58 |
刊行月 (month) |
11 |
出版年 (year) |
2018 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id495, title = {Hardware Architecture for Fast General Object Detection using Aggregated Channel Features}, author = {K. Mitsunari and J. Yu and M. Hashimoto}, journal = {Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)}, pages = {55-58}, month = {11}, year = {2018}, } |