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K. Mitsunari, J. Yu, T. Onoye, and M. Hashimoto, "Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E101-A(9), pp. 1298--1307, September 2018.
ID 481
分類 論文誌
タグ architecture decision detection ensemble hardware high-speed object tree
表題 (title) Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
表題 (英文)
著者名 (author) K. Mitsunari,J. Yu,T. Onoye,M. Hashimoto
英文著者名 (author) K. Mitsunari,J. Yu,T. Onoye,M. Hashimoto
キー (key) K. Mitsunari,J. Yu,T. Onoye,M. Hashimoto
定期刊行物名 (journal) IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
定期刊行物名 (英文)
巻数 (volume) E101-A
号数 (number) 9
ページ範囲 (pages) 1298--1307
刊行月 (month) 9
出版年 (year) 2018
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル pdf (application/pdf) [一般閲覧可]
BiBTeXエントリ
@article{id481,
         title = {Hardware Architecture for High-Speed Object Detection using Decision Tree Ensemble},
        author = {K. Mitsunari and J. Yu and T. Onoye and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E101-A},
        number = {9},
         pages = {1298--1307},
         month = {9},
          year = {2018},
}