Detail of a work
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M. Hashimoto and H. Onodera, "Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E84-A(11), pp. 2769-2777, November 2001. | |
ID | 25 |
分類 | 論文誌 |
タグ | |
表題 (title) |
Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design |
表題 (英文) |
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著者名 (author) |
M. Hashimoto,H. Onodera |
英文著者名 (author) |
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キー (key) |
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定期刊行物名 (journal) |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences |
定期刊行物名 (英文) |
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巻数 (volume) |
E84-A |
号数 (number) |
11 |
ページ範囲 (pages) |
2769-2777 |
刊行月 (month) |
11 |
出版年 (year) |
2001 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | 17.pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id25, title = {Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design}, author = {M. Hashimoto and H. Onodera}, journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences}, volume = {E84-A}, number = {11}, pages = {2769-2777}, month = {11}, year = {2001}, } |