: M. Hashimoto and H. Onodera, A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing, December 2000.
Detail of a work
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| M. Hashimoto and H. Onodera, "A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing," In Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 34-37, December 2000. | |
| ID | 82 |
| 分類 | 国際会議 |
| タグ | |
| 表題 (title) |
A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing |
| 表題 (英文) |
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| 著者名 (author) |
M. Hashimoto,H. Onodera |
| 英文著者名 (author) |
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| 編者名 (editor) |
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| 編者名 (英文) |
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| キー (key) |
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| 書籍・会議録表題 (booktitle) |
Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) |
| 書籍・会議録表題(英文) |
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| 巻数 (volume) |
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| 号数 (number) |
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| ページ範囲 (pages) |
34-37 |
| 組織名 (organization) |
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| 出版元 (publisher) |
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| 出版元 (英文) |
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| 出版社住所 (address) |
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| 刊行月 (month) |
12 |
| 出版年 (year) |
2000 |
| 採択率 (acceptance) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@inproceedings{id82,
title = {A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing},
author = {M. Hashimoto and H. Onodera},
booktitle = {Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)},
pages = {34-37},
month = {12},
year = {2000},
}
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