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M. Hashimoto, H. Onodera, and K. Tamaru, "A Power Optimization Method Considering Glitch Reduction by Gate Sizing," In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 221-226, August 1998. | |
ID | 87 |
分類 | 国際会議 |
タグ | |
表題 (title) |
A Power Optimization Method Considering Glitch Reduction by Gate Sizing |
表題 (英文) |
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著者名 (author) |
M. Hashimoto,H. Onodera,K. Tamaru |
英文著者名 (author) |
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編者名 (editor) |
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編者名 (英文) |
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キー (key) |
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書籍・会議録表題 (booktitle) |
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) |
書籍・会議録表題(英文) |
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巻数 (volume) |
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号数 (number) |
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ページ範囲 (pages) |
221-226 |
組織名 (organization) |
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出版元 (publisher) |
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出版元 (英文) |
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出版社住所 (address) |
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刊行月 (month) |
8 |
出版年 (year) |
1998 |
採択率 (acceptance) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | 48.pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@inproceedings{id87, title = {A Power Optimization Method Considering Glitch Reduction by Gate Sizing}, author = {M. Hashimoto and H. Onodera and K. Tamaru}, booktitle = {Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)}, pages = {221-226}, month = {8}, year = {1998}, } |