: M. Hashimoto, H. Onodera, and K. Tamaru, A Power Optimization Method Considering Glitch Reduction by Gate Sizing, August 1998.
Detail of a work
| Tweet | |
| M. Hashimoto, H. Onodera, and K. Tamaru, "A Power Optimization Method Considering Glitch Reduction by Gate Sizing," In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 221-226, August 1998. | |
| ID | 87 |
| 分類 | 国際会議 |
| タグ | |
| 表題 (title) |
A Power Optimization Method Considering Glitch Reduction by Gate Sizing |
| 表題 (英文) |
|
| 著者名 (author) |
M. Hashimoto,H. Onodera,K. Tamaru |
| 英文著者名 (author) |
|
| 編者名 (editor) |
|
| 編者名 (英文) |
|
| キー (key) |
|
| 書籍・会議録表題 (booktitle) |
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) |
| 書籍・会議録表題(英文) |
|
| 巻数 (volume) |
|
| 号数 (number) |
|
| ページ範囲 (pages) |
221-226 |
| 組織名 (organization) |
|
| 出版元 (publisher) |
|
| 出版元 (英文) |
|
| 出版社住所 (address) |
|
| 刊行月 (month) |
8 |
| 出版年 (year) |
1998 |
| 採択率 (acceptance) |
|
| URL |
|
| 付加情報 (note) |
|
| 注釈 (annote) |
|
| 内容梗概 (abstract) |
|
| 論文電子ファイル | 48.pdf (application/pdf) [一般閲覧可] |
| BiBTeXエントリ |
@inproceedings{id87,
title = {A Power Optimization Method Considering Glitch Reduction by Gate Sizing},
author = {M. Hashimoto and H. Onodera and K. Tamaru},
booktitle = {Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)},
pages = {221-226},
month = {8},
year = {1998},
}
|