Detail of a work
Tweet | |
C. Hsu, M. P. Lin, and M. Hashimoto, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Proceedings of System Level Interconnect Prediction (SLIP) Workshop, June 2016. | |
ID | 432 |
分類 | 国際会議 |
タグ | |
表題 (title) |
Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits |
表題 (英文) |
|
著者名 (author) |
C.-C. Hsu,M. P.-H. Lin,M. Hashimoto |
英文著者名 (author) |
|
キー (key) |
|
定期刊行物名 (journal) |
Proceedings of System Level Interconnect Prediction (SLIP) Workshop |
定期刊行物名 (英文) |
|
巻数 (volume) |
|
号数 (number) |
|
ページ範囲 (pages) |
|
刊行月 (month) |
6 |
出版年 (year) |
2016 |
Impact Factor (JCR) |
|
URL |
|
付加情報 (note) |
|
注釈 (annote) |
|
内容梗概 (abstract) |
|
論文電子ファイル | 229.pdf (application/pdf) [一般閲覧可] |
BiBTeXエントリ |
@article{id432, title = {Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits}, author = {C.-C. Hsu and M. P.-H. Lin and M. Hashimoto}, journal = {Proceedings of System Level Interconnect Prediction (SLIP) Workshop}, month = {6}, year = {2016}, } |