: C. Hsu, M. Hashimoto, and P. Lin, Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits, June 2017.
Detail of a work
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| C. Hsu, M. Hashimoto, and P. Lin, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Integration, the VLSI Journal, 58, pp. 236--244, June 2017. | |
| ID | 445 |
| 分類 | 論文誌 |
| タグ | |
| 表題 (title) |
Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits |
| 表題 (英文) |
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| 著者名 (author) |
C.-C. Hsu,M. Hashimoto,P.-H. Lin |
| 英文著者名 (author) |
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| キー (key) |
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| 定期刊行物名 (journal) |
Integration, the VLSI Journal |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
58 |
| 号数 (number) |
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| ページ範囲 (pages) |
236--244 |
| 刊行月 (month) |
6 |
| 出版年 (year) |
2017 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 233.pdf (application/pdf) [一般閲覧可] |
| BiBTeXエントリ |
@article{id445,
title = {Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits},
author = {C.-C. Hsu and M. Hashimoto and P.-H. Lin},
journal = {Integration, the VLSI Journal},
volume = {58},
pages = {236--244},
month = {6},
year = {2017},
}
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