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論文誌: [1] C.-C. Hsu, M. Hashimoto, and P.-H. Lin, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Integration, the VLSI Journal, volume 58, pages 236--244, June 2017. [233.pdf]
国際会議: [1] C.-C. Hsu, M. P.-H. Lin, and M. Hashimoto, "Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits," Proceedings of System Level Interconnect Prediction (SLIP) Workshop, June 2016. [229.pdf]