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T. Tanaka, T. Uezono, K. Suenaga, and M. Hashimoto, "In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 採録済.
ID 693
分類 論文誌
タグ behavior-derived detection error hardware in-situ models net petri sequences specification-derived state
表題 (title) In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences
表題 (英文)
著者名 (author) Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto
英文著者名 (author) ,,,
キー (key) ,,,
定期刊行物名 (journal) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
定期刊行物名 (英文)
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号数 (number)
ページ範囲 (pages)
刊行月 (month) 0
出版年 (year) (to appear)
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内容梗概 (abstract)
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BiBTeXエントリ
@article{id693,
         title = {In-Situ Hardware Error Detection Using Specification-Derived Petri Net Models and Behavior-Derived State Sequences},
        author = {Tomonari Tanaka and  Takumi Uezono and  Kohei Suenaga and  Masanori Hashimoto},
       journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
         month = {0},
          year = {(to appear)},
}