Academic Journal
|
, B. Li, , , , M. Hashimoto, U. Schlichtmann
|
Virtualsync+: Timing Optimization with Virtual Synchronization
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 41(12)
|
5526-5540
|
December 2022
|
| pdf
|
Academic Journal
|
T. Nakayama, M. Hashimoto
|
Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 102-A(7)
|
914--917
|
July 2019
|
| pdf
|
Academic Journal
|
Y. Masuda, M. Hashimoto
|
MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 102-A(7)
|
867--877
|
July 2019
|
| pdf
|
Academic Journal
|
B. Li, M. Hashimoto, U. Schlichtmann
|
From Process Variations to Reliability: a Survey of Timing of Digital Circuits in the Nanometer Era (Invited)
|
IPSJ Transactions on System LSI Design Methodology
| 11
|
2--15
|
February 2018
|
|
|
Academic Journal
|
Y. Masuda, T. Onoye, M. Hashimoto
|
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E100-A(7)
|
1452--1463
|
July 2017
|
| pdf
|
Academic Journal
|
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices
|
IEICE Electronics Express (ELEX)
| 10(5)
|
|
April 2013
|
| 184.pdf
|
Academic Journal
|
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto
|
Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2399--2408
|
December 2010
|
| 148.pdf
|
Academic Journal
|
T. Enami, S. Ninomiya, M. Hashimoto
|
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 28(4)
|
541 - 553
|
April 2009
|
| 118.pdf
|
Academic Journal
|
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
|
Timing Analysis Considering Temporal Supply Voltage Fluctuation
|
IEICE Trans. on Information and Systems
| E91-D(3)
|
655--660
|
March 2008
|
| 101.pdf
|
Academic Journal
|
T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, M. Hashimoto
|
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3666-3670
|
December 2006
|
| 5.pdf
|
Academic Journal
|
M. Hashimoto, Y. Yamada, H. Onodera
|
Equivalent Waveform Propagation for Static Timing Analysis
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 23(4)
|
498-508
|
April 2004
|
| 20.pdf
|
International Conference
|
|
Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
|
November 2018
|
| pdf
|
International Conference
|
L. Zhang, B. Li, M. Hashimoto. U. Schlichtmann
|
VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units
|
Proceedings of Design Automation Conference (DAC)
|
|
|
June 2018
|
| pdf
|
