Academic Journal
|
, , , S. Abe, , , M. Fukuda, M. Hashimoto
|
Validating Terrestrial SER in 12-, 28- and 65-nm SRAMs Estimated by Simulation Coupled with One-Time Neutron Irradiation
|
IEEE Transactions on Nuclear Science
|
|
|
(accepted, to appear)
|
|
|
Academic Journal
|
, , , M. Hashimoto, R. Shirai
|
A Current Chopper-Assisted Magnetic Field-Based Backscatter Communication Method with WPT Overcoming Ultra-Low Coupling Coefficients
|
IEEE Sensors Journal
|
|
|
(accepted, to appear)
|
|
|
Academic Journal
|
, , , M. Hashimoto
|
An 88.5 fsrms Integrated Jitter and ‒76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector
|
IEEE Transactions on Circuits and Systems I: Regular Papers
|
|
|
(accepted, to appear)
|
| pdf
|
Academic Journal
|
, , , , , , , Y. Watanabe, S. Abe, W. Liao, M. Tampo, , , Y. Miyake, M. Hashimoto
|
Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs, and 28-nm Planar SRAMs and Register Files
|
IEEE Transactions on Nuclear Science
|
|
|
(accepted, to appear)
|
|
|
Academic Journal
|
, , , , Y. Watanabe, , , , , M. Hashimoto
|
Experimental Study of Proton-Induced Radiation Effects on DDR5 Modules
|
IEEE Transactions on Nuclear Science
|
|
|
(accepted, to appear)
|
|
|
Academic Journal
|
R. Shirai, , M. Hashimoto
|
Analytical Equivalent Circuit Extraction of Foreign Metal Objects in WPT Systems
|
IEEE Access
| 12
|
172075-172087
|
November 2024
|
| pdf
|
Academic Journal
|
, Y. Watanabe, S. Manabe, W. Liao, M. Hashimoto, S. Abe, M. Tampo, Y. Miyake
|
Impact of Irradiation Side on Muon-Induced Single Event Upsets in 65-nm Bulk SRAMs
|
IEEE Transactions on Nuclear Science
| 71(4)
|
912-920
|
April 2024
|
| pdf
|
Academic Journal
|
, , , , , , M. Hashimoto
|
Reliability Exploration of System-On-Chip with Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks
|
IEEE Transactions on Circuits and Systems I: Regular Papers
| 70(10)
|
3978 -- 3991
|
October 2023
|
| pdf
|
Academic Journal
|
S. Abe, M. Hashimoto, W. Liao, T. Kato, , , H. Matsuyama, T. Sato, K. Kobayashi, Y. Watanabe
|
A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing
|
IEEE Transactions on Nuclear Science
| 70(8)
|
1652 -- 1657
|
August 2023
|
| pdf
|
Academic Journal
|
, , , , , M. Hashimoto
|
A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier
|
IEEE Transactions on Circuits and Systems II
| 70(6)
|
2246 - 2250
|
June 2023
|
| pdf
|
Academic Journal
|
Y. Zhang, , , , M. Hashimoto
|
Vulnerability Estimation of DNN Model Parameters with Few Fault Injections
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E106-A(3)
|
523-531
|
March 2023
|
| pdf
|
Academic Journal
|
, M. Hashimoto
|
B2N2: Resource Efficient Bayesian Neural Network Accelerator Using Bernoulli Sampler on FPGA
|
Integration, the VLSI Journal
| 89
|
1-8
|
March 2023
|
| pdf
|
Academic Journal
|
A. Lopez, , M. Hashimoto, , J. Yu
|
Recurrent Residual Networks Contain Stronger Lottery Tickets
|
IEEE Access
| 11
|
16588 - 16604
|
February 2023
|
| pdf
|
Academic Journal
|
, B. Li, , , , M. Hashimoto, U. Schlichtmann
|
Virtualsync+: Timing Optimization with Virtual Synchronization
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 41(12)
|
5526-5540
|
December 2022
|
| pdf
|
Academic Journal
|
|
Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation
|
Japanese Journal of Applied Physics
| 61(SM0804)
|
|
October 2022
|
| pdf
|
Academic Journal
|
D. Liang, J. Shiomi, N. Miura, M. Hashimoto, H. Awano
|
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter
|
IEICE Trans. on Information and Systems
| 105-D(7)
|
1273--1282
|
July 2022
|
| pdf
|
Academic Journal
|
, N. Banno, M. Miyamura, , K. Okamoto, , N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
|
Via-Switch FPGA: 65nm CMOS Implementation and Evaluation
|
IEEE Journal of Solid-State Circuits
| 57(7)
|
2250-2262
|
July 2022
|
| pdf
|
Academic Journal
|
, Y. Masuda, , , J. Chen, M. Hashimoto
|
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E105-A(3)
|
497--508
|
March 2022
|
| pdf
|
Academic Journal
|
, M. Hashimoto
|
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 105-A(3)
|
509--517
|
March 2022
|
| pdf
|
Academic Journal
|
, W. Liao, M. Hashimoto, Y. Mitsuyama
|
Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior
|
IEEE Transactions on Nuclear Science
| 69(1)
|
35--42
|
January 2022
|
| pdf
|
Academic Journal
|
, Y. Zhang, , , , M. Hashimoto
|
Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow
|
IEEE Transactions on Nuclear Science
| 68(8)
|
1668--1674
|
August 2021
|
| pdf
|
Academic Journal
|
T. Kato, M. Tampo, , , H. Matsuyama, M. Hashimoto, Y. Miyake
|
Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha Particles
|
IEEE Transactions on Nuclear Science
| 68(7)
|
1436-1444
|
July 2021
|
| pdf
|
Academic Journal
|
W. Liao, , S. Abe, Y. Mitsuyama, M. Hashimoto
|
Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM
|
IEEE Transactions on Nuclear Science
| 68(6)
|
1228-1234
|
June 2021
|
| pdf
|
Academic Journal
|
R. Shirai, Y. Itoh, M. Hashimoto
|
Make It Trackable: an Instant Magnetic Tracking System with Coil-Free Tiny Trackers
|
IEEE Access
| 9
|
26616 - 26632
|
February 2021
|
| pdf
|
Academic Journal
|
R. Doi, , T. Sakamoto, M. Hashimoto
|
A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 103-A(12)
|
1447--1455
|
December 2020
|
| pdf
|
Academic Journal
|
J. Chen, M. Hashimoto
|
A Frequency-Dependent Target Impedance Method Fulfilling Voltage Drop Constraints in Multiple Frequency Ranges
|
IEEE Transactions on Components, Packaging and Manufacturing Technology
| 10(11)
|
1769 -- 1781
|
November 2020
|
| pdf
|
Academic Journal
|
R. Doi, J. Yu, M. Hashimoto
|
Sneak Path Free Reconfiguration with Minimized Programming Steps for Via-Switch Crossbar Based FPGA
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 39(10)
|
2572--2587
|
October 2020
|
| pdf
|
Academic Journal
|
, Y. Masuda, J. Chen, J. Yu, M. Hashimoto
|
Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training
|
Integration, the VLSI Journal
| 74
|
19--31
|
September 2020
|
| pdf
|
Academic Journal
|
, S. Manabe, Y. Watanabe, , W. Liao, M. Hashimoto, S. Abe, , , Y. Miyake
|
Measurement of Single-Event Upsets in 65-nm SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF
|
IEEE Transactions on Nuclear Science
| 67(7)
|
1599 -- 1605
|
July 2020
|
| pdf
|
Academic Journal
|
T. Kato, M. Hashimoto, H. Matsuyama
|
Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs with Comparison to 20-nm Planar SRAMs
|
IEEE Transactions on Nuclear Science
| 67(7)
|
1485 -- 1493
|
July 2020
|
| pdf
|
Academic Journal
|
, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto
|
Irradiation Test of 65 nm Bulk SRAMs with DC Muon Beam at RCNP MuSIC Facility
|
IEEE Transactions on Nuclear Science
| 67(7)
|
1555 -- 1559
|
July 2020
|
| pdf
|
Academic Journal
|
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, , Y. Miyake
|
Impact of the Angle of Incidence on Negative Muon-Induced SEU Cross Sections of 65-nm Bulk and FDSOI SRAMs
|
IEEE Transactions on Nuclear Science
| 67(7)
|
1566 -- 1572
|
July 2020
|
| pdf
|
Academic Journal
|
R. Shirai, M. Hashimoto
|
DC Magnetic Field Based 3D Localization with Single Anchor Coil
|
IEEE Sensors Journal
| 20(7)
|
3902 -- 3913
|
April 2020
|
| pdf
|
Academic Journal
|
M. Hashimoto, K. Kobayashi, , S. Abe, Y. Watanabe
|
Characterizing SRAM and FF Soft Error Rates with Measurement and Simulation (Invited)
|
Integration, the VLSI Journal
| 69
|
161--179
|
November 2019
|
| pdf
|
Academic Journal
|
J. Chen, H. Kando, T. Kanamoto, , M. Hashimoto
|
A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions
|
IEEE Transactions on Components, Packaging and Manufacturing Technology
| 9(9)
|
1669--1679
|
September 2019
|
| pdf
|
Academic Journal
|
N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
|
Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA
|
IEEE Transactions on Electron Devices
| 66(8)
|
3331--3336
|
August 2019
|
| pdf
|
Academic Journal
|
S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto
|
Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs
|
IEEE Transactions on Nuclear Science
| 66(7)
|
1374 -- 1380
|
July 2019
|
| pdf
|
Academic Journal
|
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, S. Abe
|
Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs
|
IEEE Transactions on Nuclear Science
| 66(7)
|
1398 -- 1403
|
July 2019
|
| pdf
|
Academic Journal
|
T. Nakayama, M. Hashimoto
|
Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 102-A(7)
|
914--917
|
July 2019
|
| pdf
|
Academic Journal
|
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe
|
Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM
|
IEEE Transactions on Nuclear Science
| 66(7)
|
1390 -- 1397
|
July 2019
|
| pdf
|
Academic Journal
|
Y. Masuda, M. Hashimoto
|
MTTF-aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 102-A(7)
|
867--877
|
July 2019
|
| pdf
|
Academic Journal
|
W. Liao, M. Hashimoto
|
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate
|
IEICE Trans. on Electronics
| E102-C(4)
|
296--302
|
April 2019
|
| pdf
|
Academic Journal
|
H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto
|
Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture
|
IEEE Embedded Systems Letters
| 10(4)
|
119 -- 122
|
December 2018
|
| desc
|
Academic Journal
|
H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, M. Hashimoto
|
Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars
|
IEEE Transactions on VLSI Systems
| 26(12)
|
2723--2736
|
December 2018
|
| pdf
|
Academic Journal
|
Y. Masuda, T. Onoye, M. Hashimoto
|
Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving
|
IEEE Transactions on VLSI Systems
| 26(11)
|
2217--2229
|
November 2018
|
| pdf
|
Academic Journal
|
K. Mitsunari, J. Yu, T. Onoye, M. Hashimoto
|
Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E101-A(9)
|
1298--1307
|
September 2018
|
| pdf
|
Academic Journal
|
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, Y. Miyake
|
Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs
|
IEEE Transactions on Nuclear Science
| 65(8)
|
1742--1749
|
August 2018
|
| pdf
|
Academic Journal
|
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake
|
Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65-nm Bulk SRAMs
|
IEEE Transactions on Nuclear Science
| 65(8)
|
1734--1741
|
August 2018
|
| pdf
|
Academic Journal
|
B. Li, M. Hashimoto, U. Schlichtmann
|
From Process Variations to Reliability: a Survey of Timing of Digital Circuits in the Nanometer Era (Invited)
|
IPSJ Transactions on System LSI Design Methodology
| 11
|
2--15
|
February 2018
|
|
|
Academic Journal
|
R. Doi, M. Hashimoto, T. Onoye
|
An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication
|
International Journal of Embedded Systems
| 10(1)
|
22-31
|
January 2018
|
|
|
Academic Journal
|
Y. Masuda, T. Onoye, M. Hashimoto
|
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E100-A(7)
|
1452--1463
|
July 2017
|
| pdf
|
Academic Journal
|
C.-C. Hsu, M. Hashimoto, P.-H. Lin
|
Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits
|
Integration, the VLSI Journal
| 58
|
236--244
|
June 2017
|
| 233.pdf
|
Academic Journal
|
S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye
|
Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E98-A(12)
|
2607--2613
|
December 2015
|
|
|
Academic Journal
|
D. Fukuda, K. Watanabe, Y. Kanazawa, M. Hashimoto
|
Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E98-A(7)
|
1467--1474
|
July 2015
|
| 221.pdf
|
Academic Journal
|
T. Shinada, M. Hashimoto, T. Onoye
|
Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes
|
Analog Integrated Circuits and Signal Processing
|
|
|
May 2015
|
| 220.pdf
|
Academic Journal
|
S. Hirokawa, R. Harada, M. Hashimoto, T. Onoye
|
Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs
|
IEEE Transactions on Nuclear Science
| 62(2)
|
420--427
|
April 2015
|
| 219.pdf
|
Academic Journal
|
T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, M. Hashimoto
|
Exploring Well-Configurations for Minimizing Single Event Latchup
|
IEEE Transactions on Nuclear Science
| 61(6)
|
3282--3289
|
December 2014
|
| 211.pdf
|
Academic Journal
|
D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, M. Hashimoto
|
Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E97-A(12)
|
2373--2382
|
December 2014
|
| 209.pdf
|
Academic Journal
|
H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
|
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E97-A(12)
|
2518--2529
|
December 2014
|
| 210.pdf
|
Academic Journal
|
T. Amaki, M. Hashimoto, T. Onoye
|
A Process and Temperature Tolerant Oscillator-Based True Random Number Generator
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E97-A(12)
|
2393--2399
|
December 2014
|
| 208.pdf
|
Academic Journal
|
H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E97-A(7)
|
1468--1482
|
July 2014
|
| 201.pdf
|
Academic Journal
|
H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E97-A(7)
|
1483--1491
|
July 2014
|
| 202.pdf
|
Academic Journal
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E97-A(7)
|
1461--1467
|
July 2014
|
| 200.pdf
|
Academic Journal
|
H. Fuketa, R. Harada, M. Hashimoto, T. Onoye
|
Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM
|
IEEE Transactions on Device and Materials Reliability
| 14(1)
|
463 -- 470
|
March 2014
|
| 185.pdf
|
Academic Journal
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch
|
IEEE Transactions on Nuclear Science
| 60(6)
|
4362--4367
|
December 2013
|
| 197.pdf
|
Academic Journal
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment
|
IEEE Transactions on Nuclear Science
| 60(6)
|
4232--4237
|
December 2013
|
| 198.pdf
|
Academic Journal
|
D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture
|
IEEE Transactions on VLSI Systems
| 21(12)
|
2165 -- 2178
|
December 2013
|
| 177.pdf
|
Academic Journal
|
K. Shinkai, M. Hashimoto, T. Onoye
|
A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations
|
Integration, the VLSI Journal
| 46(4)
|
345--358
|
September 2013
|
| 179.pdf
|
Academic Journal
|
T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling
|
IEEE Transactions on Information Forensics and Security
| 8(8)
|
1331--1342
|
August 2013
|
| 190.pdf
|
Academic Journal
|
T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices
|
IEICE Trans. on Information and Systems
| E96-D(8)
|
1624--1631
|
August 2013
|
| 191.pdf
|
Academic Journal
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement
|
IEEE Transactions on Nuclear Science
| 60(4)
|
2630--2634
|
August 2013
|
| 180.pdf
|
Academic Journal
|
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices
|
IEICE Electronics Express (ELEX)
| 10(5)
|
|
April 2013
|
| 184.pdf
|
Academic Journal
|
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
|
Supply Noise Suppression by Triple-Well Structure
|
IEEE Transactions on VLSI Systems
| 21(4)
|
781--785
|
April 2013
|
| 169.pdf
|
Academic Journal
|
I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, T. Onoye
|
A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation
|
IEICE Electronics Express (ELEX)
| 10(4)
|
|
March 2013
|
| 182.pdf
|
Academic Journal
|
T. Amaki, M. Hashimoto, T. Onoye
|
Jitter Amplifier for Oscillator-Based True Random Number Generator
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E96-A(3)
|
684--696
|
March 2013
|
| 181.pdf
|
Academic Journal
|
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
|
Signal-Dependent Analog-To-Digital Conversion Based on MINIMAX Sampling
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E96-A(2)
|
459--468
|
February 2013
|
| 178.pdf
|
Academic Journal
|
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
|
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
IEEE Transactions on Nuclear Science
| 59(6)
|
2791--2795
|
December 2012
|
| 175.pdf
|
Academic Journal
|
S. Kimura, M. Hashimoto, T. Onoye
|
A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E95-A(12)
|
2292--2300
|
December 2012
|
| 173.pdf
|
Academic Journal
|
T. Enami, T. Sato, M. Hashimoto
|
Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E95-A(12)
|
2261--2271
|
December 2012
|
| 171.pdf
|
Academic Journal
|
Y. Takai, M. Hashimoto, T. Onoye
|
Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E95-A(12)
|
2220--2225
|
December 2012
|
| 172.pdf
|
Academic Journal
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
|
IEEE Transactions on VLSI Systems
| 20(2)
|
333--343
|
February 2012
|
| 155.pdf
|
Academic Journal
|
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E94-A(12)
|
2545--2553
|
December 2011
|
| 166.pdf
|
Academic Journal
|
K. Shinkai, M. Hashimoto, T. Onoye
|
Extracting Device-Parameter Variations with RO-Based Sensors
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E94-A(12)
|
2537--2544
|
December 2011
|
| 165.pdf
|
Academic Journal
|
T. Okumura, M. Hashimoto
|
Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E94-A(10)
|
1948--1953
|
October 2011
|
| 164.pdf
|
Academic Journal
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
IEEE Transactions on Nuclear Science
| 58(4)
|
2097--2102
|
August 2011
|
| 159.pdf
|
Academic Journal
|
H. Fuketa, D. Kuroda, M. Hashimoto, T. Onoye
|
An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion
|
IEEE Transactions on Circuits and Systems II
| 58(5)
|
299--303
|
May 2011
|
| 158.pdf
|
Academic Journal
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2417--2423
|
December 2010
|
| 149.pdf
|
Academic Journal
|
S. Ninomiya, M. Hashimoto
|
Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2441--2446
|
December 2010
|
| 150.pdf
|
Academic Journal
|
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto
|
Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2399--2408
|
December 2010
|
| 148.pdf
|
Academic Journal
|
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto
|
Gate Delay Estimation in STA under Dynamic Power Supply Noise
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(12)
|
2447--2455
|
December 2010
|
| 151.pdf
|
Academic Journal
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits
|
IEEE Transactions on VLSI Systems
| 18(7)
|
1118--1129
|
July 2010
|
| 130.pdf
|
Academic Journal
|
密山幸男, 高橋一真, 今井林太郎, 橋本昌宜, 尾上孝雄, 白川功
|
メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現
|
電子情報通信学会論文誌A
| J93-A(6)
|
397--413
|
June 2010
|
| 144.pdf
|
Academic Journal
|
K. Shinkai, M. Hashimoto, T. Onoye
|
Prediction of Self-Heating in Short Intra-Block Wires
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E93-A(3)
|
583--594
|
March 2010
|
| 135.pdf
|
Academic Journal
|
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto
|
Impact of Self-Heating in Wire Interconnection on Timing
|
IEICE Trans. on Electronics
| E93-C(3)
|
388--392
|
March 2010
|
| 136.pdf
|
Academic Journal
|
Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue
|
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 29(2)
|
250--260
|
February 2010
|
| 134.pdf
|
Academic Journal
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E92-A(12)
|
3094--3102
|
December 2009
|
| 128.pdf
|
Academic Journal
|
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto
|
An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E92-A(12)
|
3016--3023
|
December 2009
|
| 129.pdf
|
Academic Journal
|
A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto
|
Interconnect Modeling: a Physical Design Perspective (Invited)
|
IEEE Transactions on Electron Devices
| 56(9)
|
1840--1851
|
September 2009
|
| 126.pdf
|
Academic Journal
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform
|
IEEE Journal of Solid-State Circuits
| 44(6)
|
1745--1755
|
June 2009
|
| 124.pdf
|
Academic Journal
|
T. Enami, S. Ninomiya, M. Hashimoto
|
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 28(4)
|
541 - 553
|
April 2009
|
| 118.pdf
|
Academic Journal
|
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato
|
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 92-A(4)
|
990--997
|
April 2009
|
| 119.pdf
|
Academic Journal
|
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability
|
IEICE Trans. on Electronics
| E92-C(2)
|
281--285
|
February 2009
|
| 117.pdf
|
Academic Journal
|
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, C.-K. Cheng
|
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E91-A(12)
|
3474-3480
|
December 2008
|
| 113.pdf
|
Academic Journal
|
S. Abe, M. Hashimoto, T. Onoye
|
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E91-A(12)
|
3481-3487
|
December 2008
|
| 112.pdf
|
Academic Journal
|
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
|
Impact of Well Edge Proximity Effect on Timing
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E91-A(12)
|
3461-3464
|
December 2008
|
| 111.pdf
|
Academic Journal
|
Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa
|
Area-Efficient Reconfigurable Architecture for Media Processing
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E91-A(12)
|
3651-3662
|
December 2008
|
| 114.pdf
|
Academic Journal
|
渡辺 慎吾, 橋本 昌宜, 佐藤寿倫
|
タイミング歩留まり改善を目的とする演算器カスケーディング
|
情報処理学会論文誌コンピューティングシステム
| 1(2)
|
12--21
|
August 2008
|
| 108.pdf
|
Academic Journal
|
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
|
Timing Analysis Considering Temporal Supply Voltage Fluctuation
|
IEICE Trans. on Information and Systems
| E91-D(3)
|
655--660
|
March 2008
|
| 101.pdf
|
Academic Journal
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects
|
IEEE Journal of Solid-State Circuits
| 43(3)
|
718--728
|
March 2008
|
| 99.pdf
|
Academic Journal
|
高橋真吾, 築山修治, 橋本昌宜, 白川功
|
液晶ディスプレイ用サンプリング回路におけるサンプリングパルスとトランジスタサイズの最適設計手法
|
電子情報通信学会論文誌A
| J91-A(3)
|
373-382
|
March 2008
|
| 100.pdf
|
Academic Journal
|
M. Hashimoto, J. Yamaguchi, H. Onodera
|
Timing Analysis Considering Spatial Power/Ground Level Variation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E90-A(12)
|
2661-2668
|
December 2007
|
| 95.pdf
|
Academic Journal
|
M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, I. Shirakawa
|
Transistor Sizing of LCD Driver Circuit for Technology Migration
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E90-A(12)
|
2712--2717
|
December 2007
|
| 96.pdf
|
Academic Journal
|
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
|
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement
|
IEEE Transactions on Circuits and Systems II
| 54(10)
|
868--872
|
October 2007
|
| 94.pdf
|
Academic Journal
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling
|
IEICE Trans. on Electronics
| E90-C(6)
|
1267-1273
|
June 2007
|
| 88.pdf
|
Academic Journal
|
H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, M. Hashimoto
|
Proposal of Metrics for SSTA Accuracy Evaluation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E90-A(4)
|
808--814
|
April 2007
|
| 81.pdf
|
Academic Journal
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E90-A(4)
|
724--731
|
April 2007
|
| 80.pdf
|
Academic Journal
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3585-3593
|
December 2006
|
| 2.pdf
|
Academic Journal
|
S. Takahashi, S. Tsukiyama, M. Hashimoto, I. Shirakawa
|
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3538-3545
|
December 2006
|
| 1.pdf
|
Academic Journal
|
T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, M. Hashimoto
|
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3666-3670
|
December 2006
|
| 5.pdf
|
Academic Journal
|
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
|
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3560-3568
|
December 2006
|
| 3.pdf
|
Academic Journal
|
T. Sato, J. Ichimiya, N. Ono, M. Hashimoto
|
On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3491-3499
|
December 2006
|
| 4.pdf
|
Academic Journal
|
内田 好弘, 谷 貞宏, 橋本 昌宜, 築山修治, 白川 功
|
グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積もりの容易化
|
情報処理学会論文誌
| 47(6)
|
1665-1673
|
June 2006
|
|
|
Academic Journal
|
A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, H. Masuda
|
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(12)
|
3453-3462
|
December 2005
|
| 10.pdf
|
Academic Journal
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
Effects of On-Chip Inductance on Power Distribution Grid
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(12)
|
3564-3572
|
December 2005
|
| 7.pdf
|
Academic Journal
|
M. Hashimoto, T. Yamamoto, H. Onodera
|
Statistical Analysis of Clock Skew Variation in H-Tree Structure
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(12)
|
pp.3375-3381
|
December 2005
|
| 6.pdf
|
Academic Journal
|
T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto
|
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(12)
|
3382-3389
|
December 2005
|
| 9.pdf
|
Academic Journal
|
T. Sato, M. Hashimoto, H. Onodera
|
Successive Pad Assignment for Minimizing Supply Voltage Drop
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A,(12)
|
3429-3436
|
December 2005
|
| 8.pdf
|
Academic Journal
|
内田 好弘, 谷 貞宏, 橋本 昌宜, 築山修治, 白川 功
|
システム液晶のための配線容量抽出手法
|
情報処理学会論文誌
| 46(6)
|
1395-1403
|
June 2005
|
|
|
Academic Journal
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E88-A(4)
|
885-891
|
April 2005
|
| 11.pdf
|
Academic Journal
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL
|
IEICE Trans. on Electronics
| E88-C(3)
|
437-444
|
March 2005
|
| 89.pdf
|
Academic Journal
|
M. Hashimoto, H. Onodera
|
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E87-A(12)
|
3251-3257
|
December 2004
|
| 12.pdf
|
Academic Journal
|
M. Hashimoto, Y. Yamada, H. Onodera
|
Equivalent Waveform Propagation for Static Timing Analysis
|
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| 23(4)
|
498-508
|
April 2004
|
| 20.pdf
|
Academic Journal
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Representative Frequency for Interconnect R(f)L(f)C Extraction
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E86-A(12)
|
2942-2951
|
December 2003
|
| 14.pdf
|
Academic Journal
|
M. Hashimoto, M. Takahashi, H. Onodera
|
Crosstalk Noise Estimation for Generic RC Trees
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E86-A(12)
|
2965-2973
|
December 2003
|
| 13.pdf
|
Academic Journal
|
M. Hashimoto, Y. Hayashi, H. Onodera
|
Experimental Study on Cell-Base High-Performance Datapath Design
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E86-A(12)
|
3204-3207
|
December 2003
|
| 15.pdf
|
Academic Journal
|
金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜
|
遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法
|
情報処理学会論文誌
| 44(5)
|
1301-1310
|
May 2003
|
| 21.pdf
|
Academic Journal
|
M. Hashimoto, H. Onodera
|
Increase in Delay Uncertainty by Performance Optimization
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E85-A(12)
|
2799-2802
|
December 2002
|
| 16.pdf
|
Academic Journal
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
VLSI配線の伝送線路特性を考慮した駆動力決定手法
|
情報処理学会論文誌
| 43(5)
|
1338--1347
|
May 2002
|
| 63.pdf
|
Academic Journal
|
M. Hashimoto, H. Onodera
|
Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E84-A(11)
|
2769-2777
|
November 2001
|
| 17.pdf
|
Academic Journal
|
M. Hashimoto, H. Onodera
|
A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E83-A(12)
|
2558-2568
|
December 2000
|
| 18.pdf
|
Academic Journal
|
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉
|
グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法
|
情報処理学会論文誌
| 40(4)
|
1707-1716
|
April 1999
|
|
|
Academic Journal
|
M. Hashimoto, H. Onodera, K. Tamaru
|
A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E82-A(1)
|
159-166
|
January 1999
|
| 19.pdf
|
International Conference
|
, , , , , , , , W. Liao, , T. Sato, , M. Hashimoto
|
A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics
|
Digest of Symposium on VLSI Technology and Circuits
|
|
|
(accepted, to appear)
|
|
|
International Conference
|
, , , , , , , , , T. Sato, , M. Hashimoto
|
A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
|
April 2025
|
| pdf
|
International Conference
|
, W. Liao, , , , M. Hashimoto
|
HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
|
March 2025
|
| pdf
|
International Conference
|
M. Hashimoto
|
ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
379 - 384
|
January 2025
|
| pdf
|
International Conference
|
, , , M. Hashimoto
|
Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
966 - 973
|
January 2025
|
| pdf
|
International Conference
|
, M. Hashimoto, R. Shirai
|
Development of Tiny Wireless Position Tracker Enabling Real-Time Intuitive 3D Modeling
|
Proceedings of SIGGRAPH Asia
|
|
|
December 2024
|
| pdf
|
International Conference
|
M. Hashimoto
|
Characterization and Understanding of Cosmic Ray-Induced Soft Errors in SRAMs
|
Proceedings of International Meeting for Future of Electron Devices, Kansai
|
|
|
November 2024
|
| pdf
|
International Conference
|
, M. Hashimoto
|
Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators
|
International collaboration Symposium on Information, Production and Systems (ISIPS)
|
|
|
November 2024
|
|
|
International Conference
|
, , , , M. Hashimoto
|
S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators
|
Proceedings of IEEE International Conference on Computer Design (ICCD)
|
|
16-23
|
October 2024
|
| pdf
|
International Conference
|
, , , , , , , , , M. Hashimoto
|
A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping
|
Technical Digest of Asian Solid-State Circuits Conference (A-SSCC)
|
|
|
October 2024
|
| pdf
|
International Conference
|
|
Validating Terrestrial SER in 12- and 28-nm SRAMs Estimated by Simulation Coupled with One-Time Neutron Irradiation
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2024
|
|
|
International Conference
|
|
Cross-Section Prediction Method for Proton Direct Ionization Induced Single Event Upset
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2024
|
|
|
International Conference
|
|
Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2024
|
|
|
International Conference
|
, , , W. Liao, , , M. Hashimoto
|
How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --
|
Proceedings of Design Automation Conference (DAC)
|
|
|
June 2024
|
| pdf
|
International Conference
|
, T. Kato, M. Hashimoto
|
An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs
|
Proceedings of International Symposium on Reliability Physics (IRPS)
|
|
|
April 2024
|
| pdf
|
International Conference
|
, , , , S. Abe, , M. Hashimoto
|
In-Beam Activation Measurement of Muon Nuclear Capture Reaction on Si Isotopes
|
The workshop on frontier nuclear studies with gamma-ray spectrometer arrays (gamma24)
|
|
|
March 2024
|
|
|
International Conference
|
, , T. Sato, M. Hashimoto
|
Logic Locking Over TFHE for Securing User Data and Algorithms
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
|
January 2024
|
| pdf
|
International Conference
|
, M. Hashimoto
|
Performance Comparison of Memristor Crossbar-Based Analog and Fpga-Based Digital Weight-Memory-Less Neural Networks
|
Proceedings of IEEE International Conference on Rebooting Computing (ICRC)
|
|
|
December 2023
|
| pdf
|
International Conference
|
, R. Shirai, M. Hashimoto
|
A Proof-Of-Concept Prototyping of Reservoir Computing with Quantum Dots and an Image Sensor for Image Classification
|
IEEE International Conference on Rebooting Computing (ICRC)
|
|
|
December 2023
|
|
|
International Conference
|
, , , , S. Abe, , M. Hashimoto
|
Muon Nuclear Capture Reaction on 28,29,30si
|
2023 Fall meeting of APS DNP and JPS
|
|
|
November 2023
|
|
|
International Conference
|
, , , M. Hashimoto
|
Stuck Errors in Bits and Blocks in GDDR6 under High-Energy Neutron Irradiation
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2023
|
|
|
International Conference
|
, , , , , , Y. Watanabe, S. Abe, W. Liao, M. Tampo, , , , Y. Miyake, M. Hashimoto
|
Muon-Induced SEU Cross Sections of 12-nm FinFET and 28-nm Planar SRAMs
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2023
|
|
|
International Conference
|
, , S. Manabe, , , S. Abe, , M. Hashimoto, , , , , , , , , , , , , , M. Tampo, , , , Y. Watanabe
|
Nuclear Physics for Muon-Induced Soft Error
|
Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis
|
|
|
August 2023
|
|
|
International Conference
|
, M. Hashimoto
|
Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication
|
Proceedings of International Symposium on On-Line Testing and Robust System Design (IOLTS)
|
|
|
July 2023
|
| pdf
|
International Conference
|
, , , S. Abe, , M. Hashimoto
|
Study of Muon Capture Reaction on Si Via In-Beam Muon Activation
|
Advances in Radioactive Isotope Science (ARIS)
|
|
|
June 2023
|
|
|
International Conference
|
, , S. Abe, W. Liao, S. Manabe, , M. Hashimoto
|
Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
March 2023
|
| pdf
|
International Conference
|
, R. Shirai, M. Hashimoto
|
Toward Instant 3D Modeling: Highly Parallelizable Shape Reproduction Method for Soft Object Containing Numerous Tiny Position Trackers
|
Proceedings of International Conference on Intelligent User Interfaces (IUI)
|
|
|
March 2023
|
| pdf
|
International Conference
|
, , , S. Abe, , M. Hashimoto
|
Study of Muon Capture Reaction on Si Via In-Beam Muon Activation
|
Topical Workshops on Modern Aspects of Nuclear Structure
|
|
|
February 2023
|
|
|
International Conference
|
, , , S. Abe, , M. Hashimoto
|
Measurement of Muon-Induced Nuclear Transmutation for Si Isotopes
|
Trans-scale Quantum Science Institute
|
|
|
November 2022
|
|
|
International Conference
|
, , , , , M. Hashimoto
|
Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2022
|
| pdf
|
International Conference
|
, K. Kobayashi, M. Hashimoto
|
Single Bit Upsets Versus Burst Errors of Stacked-Capacitor DRAMs Induced by High-Energy Neutron -SECDED Is No Longer Effective-
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2022
|
|
|
International Conference
|
S. Abe, M. Hashimoto, W. Liao, T. Kato, , , H. Matsuyama, T. Sato, K. Kobayashi, Y. Watanabe
|
A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2022
|
|
|
International Conference
|
M. Hashimoto, Y. Zhang
|
Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards
|
Proceedings of International Conference on Solid State Devices and Materials (SSDM)
|
|
|
September 2022
|
|
|
International Conference
|
, , Y. Hayashi, , M. Hashimoto, T. Sato
|
SASIMI: Evaluation Board for EM Information Leakage from Large Scale Cryptographic Circuits
|
IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity
|
|
|
August 2022
|
| pdf
|
International Conference
|
M. Tanaka, J. Yu, , , M. Hashimoto
|
Investigating Small Device Implementation of FRET-Based Optical Reservoir Computing
|
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)
|
|
|
August 2022
|
| pdf
|
International Conference
|
, R. Shirai, M. Hashimoto
|
DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object
|
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)
|
|
|
August 2022
|
| pdf
|
International Conference
|
R. Shirai, M. Hashimoto
|
Shape-Flexible Underwater Display System with Wirelessly Powered and Controlled Smart Leds
|
Proceedings of International Conference on Intelligent User Interfaces (IUI)
|
|
89–92
|
March 2022
|
| pdf
|
International Conference
|
Y. Zhang, , , , M. Hashimoto
|
Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
60-63
|
March 2022
|
| pdf
|
International Conference
|
R. Shirai, M. Hashimoto
|
Submarine LED: Wirelessly Powered Underwater Display Controlling Its Buoyancy
|
Proceedings of SIGGRAPH Asia
|
|
|
December 2021
|
| pdf
|
International Conference
|
A. Lopez, M. Hashimoto, , J. Yu
|
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks
|
Proceedings of British Machine Vision Conference (BMVC)
|
|
|
November 2021
|
| pdf
|
International Conference
|
|
Processor SER Estimation with ACE Bit Analysis
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2021
|
|
|
International Conference
|
, M. Hashimoto
|
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling
|
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
|
|
|
May 2021
|
| pdf
|
International Conference
|
M. Hashimoto, J. Chen
|
Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution (Invited)
|
Proceedings of China Semiconductor Technology International Conference (CSTIC)
|
|
|
March 2021
|
| pdf
|
International Conference
|
, M. Hashimoto
|
Linear Programming Based Reliable Software Performance Model Construction with Noisy CPU Performance Counter Values
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
|
March 2021
|
|
|
International Conference
|
, M. Hashimoto
|
BloomCA: a Memory Efficient Reservoir Computing Hardware Implementation Using Cellular Automata and Ensemble Bloom Filter
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
|
February 2021
|
| pdf
|
International Conference
|
T. Imagawa, J. Yu, M. Hashimoto, H. Ochi
|
MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
|
February 2021
|
| pdf
|
International Conference
|
Y. Masuda, , , , , M. Hashimoto
|
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
|
February 2021
|
| pdf
|
International Conference
|
, Y. Masuda, , , J. Chen, M. Hashimoto
|
Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
284 -- 290
|
January 2021
|
| pdf
|
International Conference
|
, , , , M. Hashimoto
|
Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing
|
Proceedings of International Test Conference (ITC)
|
|
|
November 2020
|
| pdf
|
International Conference
|
J. Chen, M. Hashimoto
|
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
|
Proceedings of International Test Conference (ITC)
|
|
|
November 2020
|
| pdf
|
International Conference
|
T. Kato, M. Tampo, , Y. Miyake, , M. Hashimoto
|
Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
November 2020
|
|
|
International Conference
|
A. Lopez, J. Yu, M. Hashimoto
|
Low-Cost Reservoir Computing Using Cellular Automata and Random Forests
|
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
|
|
|
October 2020
|
| pdf
|
International Conference
|
, Y. Zhang, , , , M. Hashimoto
|
Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2020
|
|
|
International Conference
|
Y. Zhang, , , , , M. Hashimoto
|
Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2020
|
|
|
International Conference
|
, J. Yu, M. Hashimoto
|
Memory Efficient Training Using Lookup-Table-Based Quantization for Neural Network
|
Proceedings of International Conference on Artificial Intelligence Circuits and Systems (AICAS)
|
|
|
August 2020
|
| pdf
|
International Conference
|
, R. Shirai, M. Hashimoto
|
Position and Posture Estimation of Capsule Endoscopy with a Single Wearable Coil Toward Daily Life Diagnosis
|
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)
|
|
57--60
|
August 2020
|
| pdf
|
International Conference
|
Y. Masuda, , , , , M. Hashimoto
|
Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling
|
International Workshop on Logic and Synthesis (IWLS)
|
|
|
July 2020
|
|
|
International Conference
|
, N. Banno, M. Miyamura, , K. Okamoto, , N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
|
1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy
|
Technical Digest of VLSI Symposium on Technology
|
|
|
June 2020
|
| pdf
|
International Conference
|
, M. Hashimoto
|
BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGA
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
|
April 2020
|
| pdf
|
International Conference
|
R. Doi, , T. Sakamoto, M. Hashimoto
|
Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA
|
Proceedings of Design, Automation and Test in Europe Conference (DATE)
|
|
|
April 2020
|
| pdf
|
International Conference
|
S. Abe, T. Sato, , S. Manabe, Y. Watanabe, W. Liao, , M. Hashimoto, , , Y. Miyake
|
Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets
|
Proceedings of International Symposium on Reliability Physics (IRPS)
|
|
|
April 2020
|
| pdf
|
International Conference
|
W. Liao, , Y. Mitsuyama, M. Hashimoto
|
Characterizing Energetic Dependence of Low-Energy Neutron-Induced MCUs in 65 nm Bulk SRAMs
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
April 2020
|
| pdf
|
International Conference
|
M. Hashimoto, , N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, , H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi
|
Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications
|
Technical Digest of International Solid-State Circuits Conference (ISSCC)
|
|
502--503
|
February 2020
|
| pdf
|
International Conference
|
M. Hashimoto, W. Liao
|
Soft Error and Its Countermeasures in Terrestrial Environment
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
|
January 2020
|
| pdf
|
International Conference
|
, , W. Liao, M. Hashimoto
|
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
|
January 2020
|
| pdf
|
International Conference
|
, J. Yu, M. Hashimoto
|
Distilling Knowledge for Non-Neural Networks
|
Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC)
|
|
|
November 2019
|
| pdf
|
International Conference
|
, J. Yu, M. Hashimoto
|
Training Data Reduction Using Support Vectors for Neural Networks
|
Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC)
|
|
|
November 2019
|
| pdf
|
International Conference
|
, J. Yu, M. Hashimoto
|
A Design Space Exploration Method of SoC Architecture for CNN-based AI Platform
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
|
October 2019
|
|
|
International Conference
|
, S. Manabe, Y. Watanabe, , W. Liao, M. Hashimoto, S. Abe, , , Y. Miyake
|
Measurement of Single-Event Upsets in 65-nm Bulk SRAMs under Irradiation of Spallation Neutrons at J-PARC MLF
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2019
|
|
|
International Conference
|
, W. Liao, M. Hashimoto, , S. Manabe, Y. Watanabe, S. Abe, , , Y. Miyake
|
Characterizing Neutron-Induced SDC Rate of Matrix Multiplication in Tesla P4 GPU
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2019
|
|
|
International Conference
|
, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto
|
Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2019
|
|
|
International Conference
|
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, , Y. Miyake
|
Impact of Incident Angle on Negative Muon-Induced SEU Cross Section of 65-nm Bulk SRAM
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2019
|
|
|
International Conference
|
, J. Yu, M. Hashimoto
|
Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier
|
Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
|
|
|
July 2019
|
| pdf
|
International Conference
|
, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada
|
Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA
|
Proceedings of Silicon Nanoelectronics Workshop
|
|
|
June 2019
|
| pdf
|
International Conference
|
J. Chen, M. Hashimoto
|
A Frequency-Dependent Target Impedance Method Fulfilling both Average and Dynamic Voltage Drop Constraints
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
|
June 2019
|
| pdf
|
International Conference
|
, Y. Masuda, , , M. Hashimoto
|
Activation-Aware Slack Assignment (ASA) for Mode-Wise Power Saving in High-End ISP
|
Design Automation Conference, Designer/IP Track
|
|
|
June 2019
|
|
|
International Conference
|
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, S. Abe, M. Tampo, , Y. Miyake
|
Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
April 2019
|
| pdf
|
International Conference
|
, R. Shirai, M. Hashimoto
|
Coverage-Scalable Instant Tabletop Positioning System with Self-Localizable Anchor Nodes
|
Proceedings of International Conference on Intelligent User Interfaces (IUI)
|
|
|
March 2019
|
| pdf
|
International Conference
|
K. Mitsunari, J. Yu, M. Hashimoto
|
Hardware Architecture for Fast General Object Detection Using Aggregated Channel Features
|
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
|
55-58
|
November 2018
|
| pdf
|
International Conference
|
|
Sneak Path Free Reconfiguration of Via-Switch Crossbars Based FPGA
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
|
November 2018
|
| pdf
|
International Conference
|
|
Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
|
November 2018
|
| pdf
|
International Conference
|
M. Hashimoto, W. Liao, S. Manabe, Y. Watanabe
|
Characterizing Soft Error Rates of 65-nm SOTB and Bulk SRAMs with Muon and Neutron Beams (Invited)
|
Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
|
|
|
October 2018
|
| pdf
|
International Conference
|
S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, Y. Watanabe
|
Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2018
|
|
|
International Conference
|
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, S. Abe
|
Estimation of Muon-Induced SEU Rates for 65-nm Bulk and UTBB-SOI SRAMs
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2018
|
|
|
International Conference
|
W. Liao, M. Hashimoto, S. Manabe, S. Abe, Y. Watanabe
|
Similarity Analysis on Neutron- and Negative Moun-Induced MCUs in 65-nm Bulk SRAM
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2018
|
|
|
International Conference
|
, J. Yu, M. Hashimoto
|
Adapting Soft Cascade to Mac Operations of Convolutional Neural Networks
|
Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC)
|
|
|
August 2018
|
|
|
International Conference
|
M. Hashimoto, Y. Nakazawa, R. Doi, J. Yu
|
Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)
|
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
|
|
|
July 2018
|
| pdf
|
International Conference
|
R. Doi, M. Hashimoto
|
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA
|
Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
|
|
|
July 2018
|
| pdf
|
International Conference
|
L. Zhang, B. Li, M. Hashimoto. U. Schlichtmann
|
VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units
|
Proceedings of Design Automation Conference (DAC)
|
|
|
June 2018
|
| pdf
|
International Conference
|
R. Shirai, T. Hirose, M. Hashimoto
|
A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes
|
Proceedings of International NEWCAS Conference
|
|
152--156
|
June 2018
|
| pdf
|
International Conference
|
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
|
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
|
May 2018
|
| pdf
|
International Conference
|
T. Nakayama, M. Hashimoto
|
Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature
|
Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
|
|
|
April 2018
|
| pdf
|
International Conference
|
K.-W. Lin, M. Hashimoto, Y.-L. Li
|
Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
|
March 2018
|
| pdf
|
International Conference
|
M. Hashimoto, Y. Masuda
|
MTTF-aware Design Methodology for Adaptive Voltage Scaling (Invited)
|
Proceedings of China Semiconductor Technology International Conference (CSTIC)
|
|
|
March 2018
|
| pdf
|
International Conference
|
Y. Masuda, M. Hashimoto
|
MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-Scaled Circuits
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
|
January 2018
|
| pdf
|
International Conference
|
M. Hashimoto, R. Shirai, Y. Itoh, T. Hirose
|
Toward Real-Time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)
|
Proceedings of IEEE International Conference on ASIC
|
|
1087--1091
|
October 2017
|
| pdf
|
International Conference
|
R. Shirai, T. Hirose, M. Hashimoto
|
Dedicated Antenna Less Power Efficient OOK Transmitter for mm-Cubic IoT Nodes
|
Proceedings of European Microwave Conference (EuMC)
|
|
101--104
|
October 2017
|
| pdf
|
International Conference
|
S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake
|
Momentum and Supply Voltage Dependencies of SEUs Induced by Low-Energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2017
|
|
|
International Conference
|
W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake
|
Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
October 2017
|
|
|
International Conference
|
M. Hashimoto, W. Liao, S. Hirokawa
|
Soft Error Rate Estimation with TCAD and Machine Learning (Invited)
|
Proceedings of International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
|
|
|
September 2017
|
| pdf
|
International Conference
|
K.-W. Lin, Y.-L. Li, M. Hashimoto
|
Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles
|
Proceedings of IEEE Intelligent Vehicles Symposium (IV)
|
|
1465--1470
|
June 2017
|
| pdf
|
International Conference
|
W. Liao, S. Hirokawa, R. Harada, M. Hashimoto
|
Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V --
|
Proceedings of International NEWCAS Conference
|
|
33-37
|
June 2017
|
| pdf
|
International Conference
|
R. Shirai, J. Kono, T. Hirose, M. Hashimoto
|
Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in mm^3-Class Sensor Node
|
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
|
|
124--127
|
May 2017
|
| pdf
|
International Conference
|
S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, M. Hashimoto
|
Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices
|
Proceedings of IEEE Wireless Power Transfer Conference (WPTC)
|
|
|
May 2017
|
| pdf
|
International Conference
|
K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, M. Hashimoto
|
GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction
|
Proceedings of International Conference on Intelligent User Interfaces (IUI)
|
|
173--178
|
March 2017
|
| pdf
|
International Conference
|
N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi
|
50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic
|
Technical Digest of IEEE International Electron Devices Meeting (IEDM)
|
|
|
December 2016
|
| 231.PDF
|
International Conference
|
Y. Masuda, M. Hashimoto, T. Onoye
|
Critical Path Isolation for Time-To-Failure Extension and Lower Voltage Operation
|
Proceedings of International Conference on Computer-Aided Design (ICCAD)
|
|
|
November 2016
|
| 230.pdf
|
International Conference
|
H.-Y. Su, B.-S. Wang, S.-Y. Hsieh, Y.-L. Li, I-H. Wu, C.-C. Wu, W.-C. Shih, H. Onodera, M. Hashimoto
|
Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
|
October 2016
|
|
|
International Conference
|
S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, M. Hashimoto
|
Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes
|
Proceedings of International Symposium on Antennas and Propagation (ISAP)
|
|
|
October 2016
|
| pdf
|
International Conference
|
Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, M. Hashimoto
|
Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems
|
Proceedings of International Symposium on Antennas and Propagation (ISAP)
|
|
|
October 2016
|
| 232.pdf
|
International Conference
|
S. Hirokawa, R. Harada, K. Sakuta, Y. Watanabe, M. Hashimoto
|
Multiple Sensitive Volume Based Soft Error Rate Estimation with Machine Learning
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2016
|
| pdf
|
International Conference
|
H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi
|
Novel Processor Architecture for Onboard Infrared Sensors (Invited)
|
Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV
| 9973
|
|
August 2016
|
|
|
International Conference
|
J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto
|
A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch
|
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
|
|
August 2016
|
| pdf
|
International Conference
|
Y. Masuda, M. Hashimoto, T. Onoye
|
Hardware-Simulation Correlation of Timing Error Detection Performance of Software-Based Error Detection Mechanisms
|
Proceedings of International On-Line Testing Symposium (IOLTS)
|
|
84--89
|
July 2016
|
| 228.pdf
|
International Conference
|
C.-C. Hsu, M. P.-H. Lin, M. Hashimoto
|
Latch Clustering for Minimizing Detection-To-Boosting Latency Toward Low-Power Resilient Circuits
|
Proceedings of System Level Interconnect Prediction (SLIP) Workshop
|
|
|
June 2016
|
| 229.pdf
|
International Conference
|
R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto
|
Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
|
March 2016
|
|
|
International Conference
|
Y. Masuda, M. Hashimoto, T. Onoye
|
Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
|
March 2016
|
|
|
International Conference
|
U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, B. Li
|
Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited)
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
705--711
|
January 2016
|
| 227.pdf
|
International Conference
|
N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi
|
A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-Outs
|
Technical Digest of IEEE International Electron Devices Meeting (IEDM)
|
|
32--35
|
December 2015
|
| 225.PDF
|
International Conference
|
R. Doi, M. Hashimoto, T. Onoye
|
An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication
|
Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)
|
|
|
November 2015
|
|
|
International Conference
|
Y. Masuda, M. Hashimoto, T. Onoye
|
Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise
|
Proceedings of International Conference on Computer-Aided Design (ICCAD)
|
|
315-322
|
November 2015
|
| 224.pdf
|
International Conference
|
S. Iizuka, Y. Masuda, M. Hashimoto, T. Onoye
|
Stochastic Timing Error Rate Estimation under Process and Temporal Variations
|
Proceedings of International Test Conference (ITC)
|
|
|
October 2015
|
| 223.pdf
|
International Conference
|
Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, M. Hashimoto
|
A Wireless Power Transfer System for Small-Sized Sensor Applications
|
Proceedings of International Conference on Solid State Devices and Materials (SSDM)
|
|
154--155
|
September 2015
|
|
|
International Conference
|
M. Ueno, M. Hashimoto, T. Onoye
|
Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization
|
Proceedings of International On-Line Testing Symposium (IOLTS)
|
|
188--193
|
July 2015
|
| 222.pdf
|
International Conference
|
S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, Y. Watanabe
|
Neutron-Induced SEU and MCU Rate Characterization and Analysis of SOTB and Bulk SRAMs at 0.3V Operation
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2015
|
|
|
International Conference
|
M. Hashimoto
|
Run-Time Performance Adaptation: Opportunities and Challenges (Invited)
|
Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC)
|
|
|
June 2015
|
| 226.pdf
|
International Conference
|
T. Uemura, M. Hashimoto
|
Investigation of Single Event Upset and Total Ionizing Dose in FeRAM for Medical Electronic Tag
|
Proceedings of International Symposium on Reliability Physics (IRPS)
|
|
|
April 2015
|
| 216.pdf
|
International Conference
|
T. Uemura, S. Okano, T. Kato, H. Matsuyama, M. Hashimoto
|
Soft Error Immune Latch Design for 20 nm Bulk CMOS
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
April 2015
|
| 217.pdf
|
International Conference
|
T. Uemura, T. Kato, S. Okano, H. Matsuyama, M. Hashimoto
|
Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM
|
Proceedings of International Symposium on Reliability Physics (IRPS)
|
|
|
April 2015
|
| 215.pdf
|
International Conference
|
S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, T. Onoye
|
3D Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method
|
Proceedings of Virtual Reality Conference (VR)
|
|
|
March 2015
|
| 218.pdf
|
International Conference
|
M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, H. Onodera
|
Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
14--15
|
January 2015
|
| 213.pdf
|
International Conference
|
S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye
|
Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
731--736
|
January 2015
|
| 214.pdf
|
International Conference
|
T. Amaki, M. Hashimoto, T. Onoye
|
An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
4--5
|
January 2015
|
| 212.pdf
|
International Conference
|
M. Hashimoto
|
Opportunities and Verification Challenges of Run-Time Performance Adaptation (Invited)
|
Proceedings of Asian Test Symposium (ATS)
|
|
248--253
|
November 2014
|
| 206.pdf
|
International Conference
|
M. Hashimoto
|
Stochastic Verification of Run-Time Performance Adaptation with Field Delay Testing (Invited)
|
Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS)
|
|
751--754
|
November 2014
|
| 207.pdf
|
International Conference
|
M. Hashimoto
|
Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited)
|
Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
|
|
|
October 2014
|
| 205.pdf
|
International Conference
|
A. Iokibe, M. Hashimoto, T. Onoye
|
Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground
|
Proceedings of International Conference on Sensing Technology (ICST)
|
|
188--193
|
September 2014
|
| 204.pdf
|
International Conference
|
R. Harada, S. Hirokawa, M. Hashimoto
|
Measurement of Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4 V SRAMs
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2014
|
|
|
International Conference
|
T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, M. Hashimoto
|
Optimizing Well-Configuration for Minimizing Single Event Latchup
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2014
|
|
|
International Conference
|
T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, K. Hatanaka
|
Preventing Single Event Latchup with Deep P-Well on P-Substrate
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
June 2014
|
| 203.pdf
|
International Conference
|
M. Ueno, M. Hashimoto, T. Onoye
|
Trace-Based Fault Localization with Supply Voltage Sensor
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
77--81
|
March 2014
|
|
|
International Conference
|
H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye
|
Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design
|
Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)
|
|
|
December 2013
|
| 199.pdf
|
International Conference
|
D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera
|
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing
|
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
|
313--316
|
November 2013
|
| 196.pdf
|
International Conference
|
J. Kono, M. Hashimoto, T. Onoye
|
Feasibility Evaluation of Near-Field Communication in Clay with 1-mm^3 Antenna
|
Proceedings of Asia-Pacific Microwave Conference (APMC)
|
|
1121--1123
|
November 2013
|
| 194.pdf
|
International Conference
|
R. Harada, M. Hashimoto, T. Onoye
|
NBTI Characterization Using Pulse-Width Modulation
|
IEEE/ACM Workshop on Variability Modeling and Characterization
|
|
|
November 2013
|
|
|
International Conference
|
S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, T. Onoye
|
Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing
|
Proceedings of International Conference on Computer-Aided Design (ICCAD)
|
|
107--114
|
November 2013
|
| 193.PDF
|
International Conference
|
T. Amaki, M. Hashimoto, T. Onoye
|
A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction
|
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
|
133--136
|
November 2013
|
| 195.pdf
|
International Conference
|
M. Hashimoto
|
Soft Error Immunity of Subthreshold SRAM (Invited)
|
Proceedings of IEEE International Conference on ASIC
|
|
91--94
|
October 2013
|
| 192.pdf
|
International Conference
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2013
|
|
|
International Conference
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2013
|
|
|
International Conference
|
T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto
|
Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2013
|
|
|
International Conference
|
T. Shinada, M. Hashimoto, T. Onoye
|
Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes
|
Proceedings of International NEWCAS Conference
|
|
|
June 2013
|
| 188.pdf
|
International Conference
|
M. Ueno, M. Hashimoto, T. Onoye
|
Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures
|
Proceedings of Reconfigurable Architectures Workshop (RAW)
|
|
301--305
|
May 2013
|
| 187.pdf
|
International Conference
|
Y. Higuchi, K. Shinkai, M. Hashimoto, R. Rao, S. Nassif
|
Extracting Device-Parameter Variations Using a Single Sensitivity-Configurable Ring Oscillator
|
Proceedings of IEEE European Test Symposium (ETS)
|
|
106--111
|
May 2013
|
| 186.pdf
|
International Conference
|
M. Hashimoto
|
Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited)
|
China Semiconductor Technology International Conference (CSTIC)
|
|
1079--1084
|
March 2013
|
| 183.pdf
|
International Conference
|
D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices
|
Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)
|
|
|
December 2012
|
| 174.pdf
|
International Conference
|
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
|
Signal-Dependent Analog-To-Digital Converter Based on MINIMAX Sampling
|
Proceedings of International SoC Design Conference (ISOCC)
|
|
120 -- 123
|
November 2012
|
| 176.pdf
|
International Conference
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement
|
Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)
|
|
|
September 2012
|
|
|
International Conference
|
T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture
|
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
|
|
August 2012
|
| 170.pdf
|
International Conference
|
R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe
|
Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
IEEE Nuclear and Space Radiation Effects Conference (NSREC)
|
|
|
July 2012
|
|
|
International Conference
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
SET Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
|
April 2012
|
| 168.PDF
|
International Conference
|
S. Kimura, M. Hashimoto, T. Onoye
|
Body Bias Clustering for Low Test-Cost Post-Silicon Tuning
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
283--289
|
February 2012
|
| 167.pdf
|
International Conference
|
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture
|
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
|
189--194
|
September 2011
|
| 162.pdf
|
International Conference
|
T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
NBTI Mitigation by Giving Random Scan-In Vectors During Standby Mode
|
Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS)
|
|
152--161
|
September 2011
|
|
|
International Conference
|
Y. Takai, M. Hashimoto, T. Onoye
|
Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
|
September 2011
|
| 163.pdf
|
International Conference
|
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
|
Signal-Dependent Analog-To-Digital Conversion Based on MINIMAX Sampling
|
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)
|
|
|
August 2011
|
| 161.pdf
|
International Conference
|
M. Hashimoto, H. Fuketa
|
Adaptive Performance Compensation with On-Chip Variation Monitoring (Invited)
|
Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)
|
|
|
August 2011
|
| 160.pdf
|
International Conference
|
T. Amaki, M. Hashimoto, T. Onoye
|
An Oscillator-Based True Random Number Generator with Jitter Amplifier
|
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
|
|
725--728
|
May 2011
|
| 157.pdf
|
International Conference
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
253--257
|
April 2011
|
| 156.PDF
|
International Conference
|
S. Kimura, M. Hashimoto, T. Onoye
|
Body Bias Clustering for Low Test-Cost Post-Silicon Tuning
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
46--51
|
April 2011
|
|
|
International Conference
|
D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability
|
IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)
|
|
|
March 2011
|
|
|
International Conference
|
K. Shinkai, M. Hashimoto, T. Onoye
|
Extracting Device-Parameter Variations with RO-Based Sensors
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
13--18
|
March 2011
|
|
|
International Conference
|
K. Shinkai, M. Hashimoto
|
Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
683--688
|
January 2011
|
| 152.pdf
|
International Conference
|
M. Hashimoto
|
Run-Time Adaptive Performance Compensation Using On-Chip Sensors (Invited)
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
285--290
|
January 2011
|
| 154.pdf
|
International Conference
|
T. Amaki, M. Hashimoto, T. Onoye
|
Jitter Amplifier for Oscillator-Based True Random Number Generator
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
81--82
|
January 2011
|
| 153.pdf
|
International Conference
|
Y. Takai, M. Hashimoto, T. Onoye
|
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation
|
Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
|
|
213--216
|
October 2010
|
| 146.pdf
|
International Conference
|
T. Okumura, M. Hashimoto
|
Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
|
September 2010
|
| 147.pdf
|
International Conference
|
T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling
|
Proceedings of International Workshop on Information Security Applications (WISA)
|
|
107-121
|
August 2010
|
|
|
International Conference
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM
|
Proceedings of International Reliability Physics Symposium (IRPS)
|
|
213--217
|
May 2010
|
| 140.PDF
|
International Conference
|
S. Abe, K. Shinkai, M. Hashimoto, T. Onoye
|
Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors
|
ACM Great Lake Symposium on VLSI (GLSVLSI)
|
|
197--202
|
May 2010
|
| 143.pdf
|
International Conference
|
Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye
|
Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO
|
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
|
|
19--20
|
May 2010
|
| 139.pdf
|
International Conference
|
D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye
|
A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation
|
Proceedings of IEEE COOL Chips
|
|
190
|
April 2010
|
| 145.pdf
|
International Conference
|
H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
646--651
|
March 2010
|
| 137.pdf
|
International Conference
|
R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
839--844
|
March 2010
|
| 138.pdf
|
International Conference
|
S. Abe, K. Shinkai, M. Hashimoto, T. Onoye
|
Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
89--94
|
March 2010
|
|
|
International Conference
|
T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto
|
Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation
|
ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
41--46
|
March 2010
|
|
|
International Conference
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
361 -- 362
|
January 2010
|
| 131.pdf
|
International Conference
|
T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto
|
Gate Delay Estimation in STA under Dynamic Power Supply Noise
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
775 -- 780
|
January 2010
|
| 132.pdf
|
International Conference
|
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
|
Soft Error Resilient VLSI Architecture for Signal Processing
|
Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)
|
|
183--186
|
December 2009
|
| 142.pdf
|
International Conference
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
215--218
|
September 2009
|
| 127.pdf
|
International Conference
|
S. Ninomiya, M. Hashimoto
|
Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving SSTA Accuracy
|
Proceedings of IEEE International SOC Conference (SOCC)
|
|
337--340
|
September 2009
|
| 141.pdf
|
International Conference
|
D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
|
Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability
|
Proceedings of International Conference on Field Programmable Logic and Applications (FPL)
|
|
186--192
|
August 2009
|
| 133.pdf
|
International Conference
|
K. Hamamoto, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits
|
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
|
|
51--56
|
August 2009
|
| 125.pdf
|
International Conference
|
D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye
|
A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability
|
Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE)
|
|
|
March 2009
|
|
|
International Conference
|
S. Watanabe, M. Hashimoto, T. Sato
|
A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
401--407
|
March 2009
|
| 122.pdf
|
International Conference
|
Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye
|
Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
236--241
|
March 2009
|
|
|
International Conference
|
K. Shinkai, M. Hashimoto
|
A Gate Delay Model Over Wide-Range of Process and Environmental Variability
|
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
79--84
|
February 2009
|
|
|
International Conference
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
266-271
|
January 2009
|
| 116.pdf
|
International Conference
|
L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, C-K Cheng
|
High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
385--390
|
January 2009
|
| 115.pdf
|
International Conference
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits
|
Proceedings of Workshop on Test Structure Design for Variability Characterization
|
|
|
November 2008
|
|
|
International Conference
|
T. Enami, M. Hashimoto, T. Sato
|
Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
420--425
|
November 2008
|
| 110.pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
|
Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process
|
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
|
397--400
|
November 2008
|
| 109.pdf
|
International Conference
|
Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, C.-K. Cheng
|
On-Chip High Performance Signaling Using Passive Compensation
|
Proceedings of IEEE International Conference on Computer Design (ICCD)
|
|
182-187
|
October 2008
|
| 123.pdf
|
International Conference
|
H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits
|
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
|
|
3--8
|
August 2008
|
| 106.pdf
|
International Conference
|
S. Takahashi, S. Tsukiyama, M. Hashimoto, I. Shirakawa
|
A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays
|
In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
|
|
|
June 2008
|
|
|
International Conference
|
S. Watanabe, M. Hashimoto, T. Sato
|
Cascading Dependent Operations for Mitigating Timing Variability
|
Proceedings. of Workshop on Quality-Aware Design (W-QUAD)
|
|
|
June 2008
|
| 105.pdf
|
International Conference
|
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --
|
Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI)
|
|
387--390
|
May 2008
|
| 104.pdf
|
International Conference
|
T. Enami, S. Ninomiya, M. Hashimoto
|
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
|
Proceedings of ACM International Symposium on Physical Design (ISPD)
|
|
160-167
|
April 2008
|
| 107.pdf
|
International Conference
|
S. Abe, M. Hashimoto, T. Onoye
|
Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
520--525
|
March 2008
|
| 102.PDF
|
International Conference
|
L. Zhang, J. Liu, H. Zhu, C-K Cheng, M. Hashimoto
|
High Performance Current-Mode Differential Logic
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
720--725
|
January 2008
|
| 98.pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
107--108
|
January 2008
|
| 97.pdf
|
International Conference
|
K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
|
A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
233-237
|
October 2007
|
|
|
International Conference
|
M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, Chung-Kuan Cheng
|
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
869--872
|
September 2007
|
| 91.pdf
|
International Conference
|
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
|
Impact of Well Edge Proximity Effect on Timing
|
Proceedings of 37th European Solid-State Device Research Conference (ESSDERC)
|
|
115--118
|
September 2007
|
| 92.pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
783--786
|
September 2007
|
| 90.pdf
|
International Conference
|
K. Shinkai, M. Hashimoto, T. Onoye
|
Future Prediction of Self-Heating in Short Intra-Block Wires
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
660-665
|
March 2007
|
| 82.PDF
|
International Conference
|
K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye
|
A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
47-53
|
November 2006
|
| 22.pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects
|
Proceedings of IEEE International Conference on Computer Design (ICCD)
|
|
70-75
|
October 2006
|
| 23.pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
721-724
|
September 2006
|
| 24.pdf
|
International Conference
|
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye
|
Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC),
|
|
861-864
|
September 2006
|
| 25.pdf
|
International Conference
|
T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, I. Shirakawa
|
Transistor Sizing of LCD Driver Circuit for Technology Migration
|
Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
| 1
|
I25-I28
|
July 2006
|
| 28.pdf
|
International Conference
|
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
|
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
|
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)
|
|
227-230
|
May 2006
|
| 65.pdf
|
International Conference
|
K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye
|
A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations
|
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
59-64
|
February 2006
|
|
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Interconnect RL Extraction at a Single Representative Frequency
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
515-520
|
January 2006
|
| 30.pdf
|
International Conference
|
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
|
Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction
|
Proceedings of International Workshop on Compact Modeling (IWCM)
|
|
51-56
|
January 2006
|
|
|
International Conference
|
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
|
A Sampling Switch Design for Liquid Crystal Displays
|
Proceedings of IEEE International Region 10 Conference
| (1C-03.3)
|
|
November 2005
|
| 64.pdf
|
International Conference
|
T. Kouno, M. Hashimoto, H. Onodera
|
Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis
|
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
|
453-456
|
November 2005
|
| 52.pdf
|
International Conference
|
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
|
Performance Prediction of On-Chip High-Throughput Global Signaling
|
Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)
|
|
79-82
|
October 2005
|
| 50.pdf
|
International Conference
|
S. Uemura, T. Miyazaki, M. Hashimoto, H. Onodera
|
Estimation of Maximum Oscillation Frequency for CMOS LCVCOs
|
Proceedings of IEEJ International Analog VLSI Workshop
|
|
|
October 2005
|
|
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
613-616
|
September 2005
|
| 27.pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
Measurement and Analysis of Delay Variation Due to Inductive Coupling
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
305-308
|
September 2005
|
| 26.pdf
|
International Conference
|
S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, I. Shirakawa
|
A Design Scheme for Sampling Switch in Active Matrix LCD
|
Proceedings of European Conference on Circuit Theory and Design
| (3e-212)
|
|
August 2005
|
| 54.pdf
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer
|
Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)
|
|
201-202
|
May 2005
|
| 49.pdf
|
International Conference
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
Effects of On-Chip Inductance on Power Distribution Grid
|
Proceedings of International Symposium on Physical Design (ISPD)
|
|
63-69
|
April 2005
|
| 46.pdf
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics
|
Proceedings of International Meeting for Future of Electron Devices, Kansai
|
|
33-34
|
April 2005
|
|
|
International Conference
|
Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa
|
Interconnect Capacitance Extraction for System LCD Circuits
|
Proceedings of Great Lakes Symposium on VLSI (GLSVLSI)
|
|
160-163
|
April 2005
|
| 29.pdf
|
International Conference
|
M. Hashimoto, T. Yamamoto, H. Onodera
|
Statistical Analysis of Clock Skew Variation in H-Tree Structure
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
402-407
|
March 2005
|
| 51.PDF
|
International Conference
|
A. Shinmyo, M. Hashimoto, H. Onodera
|
Design and Measurement of 6.4 Gbps 8:1 Multiplexer in 0.18um CMOS Process
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
D9-D10
|
January 2005
|
| 35.pdf
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Return Path Selection for Loop RL Extraction
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
1078-1081
|
January 2005
|
| 33.pdf
|
International Conference
|
M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera
|
Timing Analysis Considering Temporal Supply Voltage Fluctuation
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
1098-1101
|
January 2005
|
| 32.pdf
|
International Conference
|
T. Sato, M. Hashimoto, H. Onodera
|
Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
723-728
|
January 2005
|
| 31.pdf
|
International Conference
|
T. Sato, N. Ono, J. Ichimiya, K. Hachiya, M. Hashimoto
|
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
1074-1077
|
January 2005
|
| 34.pdf
|
International Conference
|
M. Hashimoto, A. Tsuchiya, A. Shinmyo, H. Onodera
|
Performance Prediction of On-Chip Global Signaling
|
IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)
|
|
87-100
|
November 2004
|
|
|
International Conference
|
M. Hashimoto, J. Yamaguchi, H. Onodera
|
Timing Analysis Considering Spatial Power/Ground Level Variation
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
814-820
|
November 2004
|
| 41.pdf
|
International Conference
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
LSI Power Network Analysis with On-Chip Wire Inductance
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
55-60
|
October 2004
|
|
|
International Conference
|
M. Hashimoto, A. Tsuchiya, H. Onodera
|
On-Chip Global Signaling by Wave Pipelining
|
IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP)
|
|
311-314
|
October 2004
|
| 56.pdf
|
International Conference
|
M. Hashimoto, T. Yamamoto, H. Onodera
|
Statistical Analysis of Clock Skew Variation
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
214-219
|
October 2004
|
|
|
International Conference
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL
|
IEEJ International Analog VLSI Workshop
|
|
45-50
|
October 2004
|
|
|
International Conference
|
T. Sato, M. Hashimoto, H. Onodera
|
An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
66-72
|
October 2004
|
|
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling
|
Proceedings of IEEE Custom Integrated Circuits Conference (CICC)
|
|
489-492
|
September 2004
|
| 66.pdf
|
International Conference
|
A. Shinmyo, M. Hashimoto, H. Onodera
|
Design and Optimization of CMOS Current Mode Logic Dividers
|
IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
|
|
434-435
|
August 2004
|
| 55.pdf
|
International Conference
|
M. Hashimoto, K. Fujimori, H. Onodera
|
Automatic Generation of Standard Cell Library in VDSM Technologies
|
Proceedings of International Symposium on Quality Electronic Design (ISQED)
|
|
36-41
|
March 2004
|
| 53.PDF
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Representative Frequency for Interconnect R(f)L(f)C Extraction
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
691-696
|
January 2004
|
| 37.pdf
|
International Conference
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
545-546
|
January 2004
|
| 36.pdf
|
International Conference
|
M. Hashimoto, Y. Yamada, H. Onodera
|
Equivalent Waveform Propagation for Static Timing Analysis
|
Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
|
|
169-175
|
November 2003
|
| 42.pdf
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Frequency Determination for Interconnect RLC Extraction
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
288-293
|
April 2003
|
|
|
International Conference
|
M. Hashimoto, Y. Yamada, H. Onodera
|
Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis
|
Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD)
|
|
18-23
|
April 2003
|
| 45.pdf
|
International Conference
|
Y. Yamada, M. Hashimoto, H. Onodera
|
Slew Calculation Against Diverse Gate-Input Waveforms for Accurate Static Timing Analysis
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
280-287
|
April 2003
|
|
|
International Conference
|
M. Hashimoto, K. Fujimori, H. Onodera
|
Standard Cell Libraries with Various Driving Strength Cells for 0.13, 0.18 and 0.35um Technologies
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
589-590
|
January 2003
|
| 38.pdf
|
International Conference
|
T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, M. Hashimoto
|
Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
149-155
|
January 2003
|
| 40.pdf
|
International Conference
|
M. Hashimoto, D. Hiramatsu, A. Tsuchiya, H. Onodera
|
Interconnect Structures for High-Speed Long-Distance Signal Transmission
|
Proceedings of IEEE International ASIC/SOC Conference
|
|
426-430
|
September 2002
|
| 57.pdf
|
International Conference
|
M. Hashimoto, Y. Hayashi, H. Onodera
|
Experimental Study on Cell-Base High-Performance Datapath Design
|
Proceedings of IEEE/ACM International Workshop on Logic & Synthesis (IWLS)
|
|
283-287
|
June 2002
|
|
|
International Conference
|
M. Hashimoto, M. Takahashi, H. Onodera
|
Crosstalk Noise Optimization by Post-Layout Transistor Sizing
|
Proceedings of ACM/IEEE International Symposium on Physical Design (ISPD)
|
|
126-130
|
April 2002
|
| 43.pdf
|
International Conference
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects
|
Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
377-381
|
October 2001
|
|
|
International Conference
|
M. Takahashi, M. Hashimoto, H. Onodera
|
Crosstalk Noise Estimation for Generic RC Trees
|
Proceedings of International Conference on Computer Design (ICCD)
|
|
110-116
|
September 2001
|
| 58.pdf
|
International Conference
|
H. Onodera, M. Hashimoto, T. Hashimoto
|
ASIC Design Methodology with On-Demand Library Generation
|
Proceedings of Symposium on VLSI Circuits
|
|
57-60
|
June 2001
|
| 59.pdf
|
International Conference
|
M. Hashimoto, H. Onodera
|
Increase in Delay Uncertainty by Performance Optimization
|
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
| V
|
379-382
|
May 2001
|
| 60.pdf
|
International Conference
|
M. Hashimoto, H. Onodera
|
Post-Layout Transistor Sizing for Power Reduction in Cell-Based Design
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
359-365
|
January 2001
|
| 39.pdf
|
International Conference
|
M. Hashimoto, H. Onodera
|
A Statistical Delay-Uncertainty Analysis of the Circuits Path-Balanced by Gate/Transistor Sizing
|
Proceedings of ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)
|
|
34-37
|
December 2000
|
|
|
International Conference
|
T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, H. Onodera
|
Vector Quantization Processor for Mobile Video Communication
|
Proceedings of IEEE International ASIC/SOC Conference
|
|
75-79
|
September 2000
|
| 61.pdf
|
International Conference
|
M. Hashimoto, H. Onodera
|
A Performance Optimization Method by Gate Resizing Based on Statistical Static Timing Analysis
|
Proceedings of the Ninth Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
|
|
115-121
|
April 2000
|
|
|
International Conference
|
M. Hashimoto, H. Onodera
|
A Performance Optimization Method by Gate Sizing Using Statistical Static Timing Analysis
|
Proceedings of ACM International Symposium on Physical Design (ISPD)
|
|
111-116
|
April 2000
|
| 44.pdf
|
International Conference
|
M. Hashimoto, H. Onodera, K. Tamaru
|
Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
|
Proceedings of the 36th IEEE/ACM Design Automation Conference (DAC)
|
|
446-451
|
June 1999
|
| 47.pdf
|
International Conference
|
M. Hashimoto, H. Onodera, K. Tamaru
|
A Power Optimization Method Considering Glitch Reduction by Gate Sizing
|
Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
|
|
221-226
|
August 1998
|
| 48.pdf
|
International Conference
|
M. Hashimoto, H. Onodera, K. Tamaru
|
Input Reordering for Power and Delay Optimization
|
Proceedings of IEEE International ASIC Conference and Exhibit
|
|
194-198
|
September 1997
|
| 62.pdf
|
Domestic Conference
|
, , , 阪本利司, 越智裕之, M. Hashimoto
|
メモリスタクロスバーへのニューラルネットワーク書き込みにおける write-verify 回数削減手法の検討
|
情報処理学会DAシンポジウム
|
|
|
(accepted, to appear)
|
|
|
Domestic Conference
|
, , , M. Hashimoto
|
制御フロー仕様から生成したペトリネットに基づくハードウェア誤動作検出手法
|
情報処理学会DAシンポジウム
|
|
|
(accepted, to appear)
|
|
|
Domestic Conference
|
, , 粟野皓光, , M. Hashimoto
|
Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators
|
情報処理学会DAシンポジウム
|
|
|
2024
|
|
|
Domestic Conference
|
, M. Hashimoto
|
GPU アプリケーションのスレッド間通信を用いた不正メモリアクセス検出手法の検討
|
情報処理学会DAシンポジウム
|
|
|
August 2022
|
|
|
Domestic Conference
|
, M. Hashimoto
|
RISC-Vプロセッサにおける故障注入実験及び中性子照射実験の結果比較
|
情報処理学会DAシンポジウム
|
|
|
August 2022
|
|
|
Domestic Conference
|
田上凱斗, 橋本昌宜
|
RISC-Vプロセッサに対するフォールトインジェクション実験の結果分析
|
情報処理学会DAシンポジウム
|
|
|
September 2021
|
|
|
Domestic Conference
|
稲毛康太, 橋本昌宜, 上野嶺, 粟野皓光, 本間尚文
|
モデルとプライバシーを保護するアンサンブル決定木向け秘匿推論プロトコル
|
情報処理学会 コンピュータセキュリティシンポジウム
|
|
|
October 2020
|
|
|
Domestic Conference
|
増田豊，長山凖，鄭泰禹，石原亨，籾山陽一，橋本昌宜
|
クリティカルパス・アイソレーションとビット幅削減を用いた過電圧スケーリング向け省電力設計手法
|
情報処理学会DAシンポジウム
|
|
|
August 2020
|
|
|
Domestic Conference
|
, R. Doi, M. Hashimoto
|
Rc Extraction-Free Wiring Delay Analysis Focusing on Number of On-State Switches for Via-Switch Fpga
|
情報処理学会DAシンポジウム
|
|
|
August 2019
|
|
|
Domestic Conference
|
土井龍太郎, 劉載勲, 橋本昌宜
|
ビアスイッチFPGAの部分的再構成における書き換えスイッチ数の最小化
|
情報処理学会DAシンポジウム
|
|
|
August 2019
|
|
|
Domestic Conference
|
土井龍太郎, 劉載勲, 橋本昌宜
|
ビアスイッチFPGA再構成時のスニークパス問題を回避するプログラミング順決定手法
|
情報処理学会DAシンポジウム
|
|
|
August 2018
|
|
|
Domestic Conference
|
増田豊, , , , , 橋本昌宜
|
エラー予告FFとレプリカの電圧マージン制御性能の定量的比較
|
情報処理学会DAシンポジウム
|
|
|
August 2018
|
|
|
Domestic Conference
|
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始
|
FOWLPを用いたLSIにおける再配線層上キャパシタ及びオンチップ容量の最適化
|
情報処理学会DAシンポジウム
|
|
|
August 2018
|
|
|
Domestic Conference
|
中山貴博, 橋本昌宜
|
常温で論理テスト可能な超低温動作VLSIのタイミング設計法の検討
|
情報処理学会DAシンポジウム
|
|
|
August 2017
|
|
|
Domestic Conference
|
土井龍太郎, 橋本 昌宜
|
ビアスイッチFPGAにおけるスニークパス問題のSAT符号化を用いた検証
|
情報処理学会DAシンポジウム
|
|
|
August 2017
|
|
|
Domestic Conference
|
増田豊, 橋本昌宜
|
エラー予告ベース適応的電圧制御のMTTF考慮設計手法
|
情報処理学会DAシンポジウム
|
|
|
August 2017
|
|
|
Domestic Conference
|
金本俊幾, 葛西孝己, 今井雅, 黒川敦, 橋本昌宜, 陳俊, 神藤始
|
容量配置最適化に向けた15nm世代LSI・パッケージ・ボード電源網解析モデルの構築
|
情報処理学会DAシンポジウム
|
|
|
August 2017
|
|
|
Domestic Conference
|
佐藤雅紘, 増田豊, 飯塚翔一, 尾上孝雄, 橋本昌宜
|
確率的回路寿命予測手法の計算安定性と確率取り扱いの妥当性に関する考察
|
情報処理学会DAシンポジウム
|
|
|
September 2016
|
|
|
Domestic Conference
|
増田豊, 尾上孝雄, 橋本昌宜
|
低電圧・長寿命動作に向けたクリティカルパス・アイソレーション手法
|
情報処理学会DAシンポジウム
|
|
|
September 2016
|
|
|
Domestic Conference
|
増田豊, 橋本昌宜, 尾上孝雄
|
電源ノイズ起因タイミング故障のデバッグにおけるC言語ベース故障検出手法の有効性評価
|
情報処理学会DAシンポジウム
|
|
|
August 2015
|
|
|
Domestic Conference
|
秋原 優樹, 廣瀬 哲也, 田中 勇気, 黒木 修隆, 沼 昌宏, 橋本 昌宜
|
小型センサデバイスに向けた無線給電システムの設計
|
回路とシステムワークショップ
|
|
258--263
|
August 2015
|
|
|
Domestic Conference
|
増田豊, 橋本昌宜, 尾上孝雄
|
電源ノイズ起因電気的故障を対象としたソフトウェアベース高速エラー検出手法の性能評価
|
情報処理学会DAシンポジウム
|
|
203--208
|
August 2014
|
|
|
Domestic Conference
|
飯塚翔一, 樋口裕磨, 橋本昌宜, 尾上孝雄
|
感度可変リングオシレータを用いた省面積デバイスパラメータばらつき推定手法
|
情報処理学会DAシンポジウム
|
|
15--20
|
August 2014
|
|
|
Domestic Conference
|
飯塚翔一, 水野雅文, 黒田弾, 橋本昌宜, 尾上孝雄
|
適応的速度制御における連続時間マルコフ過程を用いた故障発生時間高速評価手法
|
情報処理学会DAシンポジウム
|
|
|
August 2013
|
|
|
Domestic Conference
|
橋本昌宜
|
低電力回路技術
|
センサマイクロマシンとその応用シンポジウムプログラム
|
|
|
October 2012
|
|
|
Domestic Conference
|
城間誠, 山中俊輝, 小笠原泰弘, 金本俊幾, 成木保文, 奥村隆昌, 増田弘生, 古川且洋, 佐藤高史, 橋本昌宜, 黒川敦, 田中正和
|
微細プロセス（22nm世代）における配線コーナー設計手法の検討
|
情報処理学会DAシンポジウム
|
|
199--204
|
August 2012
|
|
|
Domestic Conference
|
小谷 憲, 増田弘生, 成木保文, 奥村隆昌, 城間 誠, 金本俊幾, 古川且洋, 山中俊輝, 小笠原泰弘, 佐藤高史, 橋本昌宜, 黒川敦, 田中正和
|
微細CMOSタイミング設計の新しいコーナー削減方法
|
情報処理学会DAシンポジウム
|
|
193--198
|
August 2012
|
|
|
Domestic Conference
|
樋口裕磨, 新開健一, 橋本昌宜, R. Rao, S. Nassif
|
感度可変リングオシレータを用いたデバイスパラメータばらつき推定
|
情報処理学会DAシンポジウム
|
|
|
August 2012
|
|
|
Domestic Conference
|
亀田敏広, 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄
|
スキャンパスを用いたNBTI劣化抑制に関する一検討
|
情報処理学会DAシンポジウム
|
|
201--206
|
September 2011
|
|
|
Domestic Conference
|
佐方剛, 成木保文, 奥村隆昌, 金本俊幾, 増田弘生, 佐藤高史, 橋本昌宜, 古川且洋, 田中正和, 山中俊輝
|
CMOSドライバ回路遅延のNBTI劣化ばらつき特性解析
|
情報処理学会DAシンポジウム
|
|
|
September 2011
|
|
|
Domestic Conference
|
増田弘生, 佐方剛, 佐藤高史, 橋本昌宜, 古川且洋, 田中正和, 山中俊輝, 金本俊幾
|
RTNを考慮した回路特性ばらつき解析方法の検討
|
情報処理学会DAシンポジウム
|
|
209--214
|
September 2010
|
|
|
Domestic Conference
|
木村修太, 橋本昌宜, 尾上孝雄
|
製造後性能補償のためのリーク・遅延相関考慮クラスタリング手法
|
情報処理学会DAシンポジウム
|
|
93--98
|
September 2010
|
|
|
Domestic Conference
|
榎並孝司, 木村修太, 橋本昌宜, 尾上孝雄
|
自己性能補償に向けたカナリアFF挿入手法
|
情報処理学会DAシンポジウム
|
|
227--232
|
September 2010
|
|
|
Domestic Conference
|
新開健一, 橋本昌宜
|
広範囲な製造・環境ばらつきに対応したゲート遅延モデル
|
情報処理学会DAシンポジウム
|
|
73--78
|
August 2009
|
|
|
Domestic Conference
|
橋本昌宜, 榎並孝司, 新開健一, 二宮進有, 阿部慎也
|
電源ノイズや製造ばらつきによるクロックジッタ・スキューを考慮した統計的タイミング解析
|
情報処理学会DAシンポジウム
|
|
79--84
|
August 2009
|
|
|
Domestic Conference
|
郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄
|
NBTIによる劣化予測におけるトランジスタ動作確率算出法の評価
|
情報処理学会DAシンポジウム
|
|
181--186
|
August 2009
|
|
|
Domestic Conference
|
佐方 剛, 黒川 敦, 奥村 隆昌, 中島 英斉, 増田 弘生, 佐藤 高史, 橋本 昌宜, 蜂屋 孝太郎, 古川 且洋, 田中 正和, 高藤 浩資, 金本 俊幾
|
製造ばらつきに起因するリーク電流変動の低減アプローチ
|
第22回 回路とシステム(軽井沢)ワークショップ
|
|
444--449
|
April 2009
|
| 120.pdf
|
Domestic Conference
|
天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄
|
マルコフモデルによるオシレータサンプリング方式真性乱数生成器の乱数品質解析
|
第22回 回路とシステム(軽井沢)ワークショップ
|
|
474---479
|
April 2009
|
| 121.pdf
|
Domestic Conference
|
更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
|
タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析
|
情報処理学会DAシンポジウム
|
|
217--222
|
August 2008
|
|
|
Domestic Conference
|
渡辺 慎吾, 橋本 昌宜, 佐藤寿倫
|
タイミング歩留まり改善を目的とする演算器カスケーディング
|
先進的計算基盤システムシンポジウム(Symposium on Advanced Computing Systems and Infrastructures; SACSIS)
|
|
115--122
|
June 2008
|
|
|
Domestic Conference
|
増田 弘生, 大川 眞一, 黄田 剛, 奥村 隆昌, 黒川 敦, 金本 俊幾, 佐藤 高史, 橋本 昌宜, 高藤 浩資, 中島 英斉, 小野 信任
|
チップ内システマティックばらつきと回路スキュー特性相関
|
第21回 回路とシステム(軽井沢)ワークショップ
|
|
617--622
|
April 2008
|
|
|
Domestic Conference
|
奥村 隆昌, 黒川 敦, 増田 弘生, 金本 俊幾, 佐藤 高史, 橋本 昌宜, 高藤 浩資, 中島 英斉, 小野 信任
|
Vth ばらつきに拠る出力遷移時間ばらつきの解析
|
第21回 回路とシステム(軽井沢)ワークショップ
|
|
299--304
|
April 2008
|
|
|
Domestic Conference
|
阿部慎也, 橋本昌宜, 尾上孝雄
|
製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価
|
情報処理学会DAシンポジウム
|
|
133-138
|
August 2007
|
|
|
Domestic Conference
|
中林 太美世, 黒川 敦, 増田 弘生, 橋本 昌宜, 佐藤 高史
|
45-65nmプロセスにおける遅延ばらつき特性の環境温度依存
|
第20回 回路とシステム(軽井沢)ワークショップ
|
|
691--696
|
April 2007
|
| 86.pdf
|
Domestic Conference
|
新開 健一, 橋本 昌宜, 尾上孝雄
|
短距離ブロック内配線の自己発熱
|
第20回 回路とシステム(軽井沢)ワークショップ
|
|
7--12
|
April 2007
|
| 83.pdf
|
Domestic Conference
|
榎並 孝司, 二宮 進有, 橋本 昌宜
|
電源ノイズの空間的相関を考慮した統計的タイミング解析
|
第20回 回路とシステム(軽井沢)ワークショップ
|
|
667--672
|
April 2007
|
| 84.pdf
|
Domestic Conference
|
橋本 昌宜
|
製造・環境ばらつきと動的性能補償を考慮したタイミング検証に向けて
|
第20回 回路とシステム(軽井沢)ワークショップ
|
|
661--666
|
April 2007
|
| 85.pdf
|
Domestic Conference
|
高藤 浩資, 小林 宏行, 小野 信任, 増田 弘生, 中島 英斉, 奥村 隆昌, 橋本 昌宜, 佐藤 高史
|
統計的STAでのスルー依存性を考慮した遅延ばらつき計算手法の提案
|
第20回 回路とシステム(軽井沢)ワークショップ
|
|
709--714
|
April 2007
|
| 87.pdf
|
Domestic Conference
|
小林宏行、小野信任、佐藤高史、岩井二郎、橋本昌宜
|
統計的STA の精度検証手法
|
情報処理学会DAシンポジウム
|
|
7-12
|
July 2006
|
|
|
Domestic Conference
|
榎並孝司、橋本昌宜、尾上孝雄
|
主成分分析による電源電圧変動の統計的モデル化手法
|
情報処理学会DAシンポジウム
|
|
205-210
|
July 2006
|
|
|
Domestic Conference
|
小林 宏行, 小野 信任, 佐藤 高史, 岩井 二郎, 橋本 昌宜
|
統計的STAの有効性の検証手法
|
第19回 回路とシステム(軽井沢)ワークショップ
|
|
553-558
|
April 2006
|
| 74.pdf
|
Domestic Conference
|
小笠原 泰弘, 橋本 昌宜, 尾上 孝雄
|
LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測
|
第19回 回路とシステム(軽井沢)ワークショップ
|
|
5-10
|
April 2006
|
| 73.pdf
|
Domestic Conference
|
新開 健一, 橋本 昌宜, 黒川 敦, 尾上 孝雄
|
電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル
|
第19回 回路とシステム(軽井沢)ワークショップ
|
|
559-564
|
April 2006
|
| 75.pdf
|
Domestic Conference
|
土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
配線の伝達特性ﾉ基づく抽出周波数決定手法
|
情報処理学会DAシンポジウム
|
|
169-174
|
August 2005
|
|
|
Domestic Conference
|
土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
オンチップ高速信号伝送における終端抵抗決定手法
|
第18回 回路とシステム(軽井沢)ワークショップ
|
|
425-430
|
April 2005
|
|
|
Domestic Conference
|
佐藤 高史, 市宮 淳次, 小野 信任, 蜂屋 孝太郎, 橋本 昌宜
|
フロアプランにおけるオンチップ熱ばらつきの解析と対策
|
情報処理学会DAシンポジウム
|
|
133-138
|
July 2004
|
|
|
Domestic Conference
|
土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
配線RL抽出におけるリターンパス選択手法
|
情報処理学会DAシンポジウム
|
|
175-180
|
July 2004
|
|
|
Domestic Conference
|
村松 篤, 橋本 昌宜, 小野寺 秀俊
|
オンチップインダクタンスを考慮したLSI電源配線網解析
|
情報処理学会DAシンポジウム
|
|
277-282
|
July 2004
|
|
|
Domestic Conference
|
金本 俊幾, 阿久津滋聖, 中林 太美世, 一宮 敬弘, 蜂屋 孝太郎, 石川 博, 室本 栄, 小林 宏行, 橋本 昌宜, 黒川 敦
|
遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価
|
情報処理学会DAシンポジウム
|
|
265-270
|
July 2004
|
|
|
Domestic Conference
|
土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---
|
第17回 回路とシステム(軽井沢)ワークショップ
|
|
567-572
|
April 2004
|
|
|
Domestic Conference
|
土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
直交配線を持つオンチップ伝送線路の特性評価
|
情報処理学会DAシンポジウム
|
|
133-138
|
July 2003
|
|
|
Domestic Conference
|
土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
配線R(f)L(f)C抽出のための代表周波数決定手法
|
第16回 回路とシステム(軽井沢)ワークショップ
|
|
61-66
|
April 2003
|
|
|
Domestic Conference
|
山口 隼司, 橋本 昌宜, 小野寺 秀俊
|
IRドロップを考慮した電源線構造の最適化手法
|
情報処理学会DAシンポジウム
|
|
253-258
|
July 2002
|
|
|
Domestic Conference
|
平松 大輔, 土谷 亮, 橋本 昌宜, 小野寺 秀俊
|
長距離高速信号伝送を可能にするVLSI配線構造の検討
|
情報処理学会DAシンポジウム
|
|
155-160
|
July 2002
|
|
|
Domestic Conference
|
林 宙輝, 橋本 昌宜, 小野寺 秀俊
|
セルベース設計環境を用いた高性能データパス設計法の検討
|
情報処理学会DAシンポジウム
|
|
113-118
|
July 2002
|
|
|
Domestic Conference
|
金本 俊幾, 佐藤 高史, 黒川 敦, 川上 善之, 岡 宏規, 北浦 智靖, 池内 敦彦, 小林 宏行, 橋本 昌宜
|
0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法
|
情報処理学会DAシンポジウム
|
|
149-154
|
July 2002
|
|
|
Domestic Conference
|
佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜
|
インダクタンスが配線遅延に及ぼす影響の定量的評価方法
|
第15回 回路とシステム(軽井沢)ワークショップ
|
|
493-498
|
April 2002
|
|
|
Domestic Conference
|
高橋 正郎, 橋本 昌宜, 小野寺 秀俊
|
隣接位置を考慮した解析的クロストークノイズ見積もり手法
|
情報処理学会DAシンポジウム
|
|
19-24
|
July 2001
|
|
|
Domestic Conference
|
橋本 昌宜, 小野寺 秀俊
|
セルベース設計における連続的トランジスタ寸法最適化による消費電力削減手法
|
情報処理学会DAシンポジウム
|
|
185-190
|
July 2000
|
|
|
Domestic Conference
|
橋本 昌宜, 小野寺 秀俊
|
静的統計遅延解析に基づいたゲート寸法最適化による回路性能最適化手法
|
第13回 回路とシステム(軽井沢)ワークショップ
|
|
137-142
|
April 2000
|
|
|
Domestic Conference
|
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉
|
グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法
|
情報処理学会DAシンポジウム
|
|
269-274
|
July 1998
|
|
|
Domestic Conference
|
橋本 昌宜, 小野寺 秀俊, 田丸 啓吉
|
入力端子接続最適化による消費電力削減手法
|
情報処理学会DAシンポジウム
|
|
99-104
|
July 1997
|
|
|
Workshop
|
, , , , 安部晋一郎, , , , , , , , , , , , , , M. Hashimoto
|
Siミューオン原子核捕獲反応による核変換分岐比の測定
|
日本物理学会 第79回年次大会
|
|
|
(accepted, to appear)
|
|
|
Workshop
|
M. Hashimoto
|
GDDR6における高エネルギー中性子照射によるスタックビット・ブロックの発生
|
宇宙科学技術連合講演会
|
|
|
October 2023
|
|
|
Workshop
|
, , , , S. Abe, , M. Hashimoto
|
ミューオン原子核捕獲反応による生成核分岐比の測定
|
第12回停止・低速RIビームを用いた核分光研究会 (12th SSRI)
|
|
|
September 2023
|
|
|
Workshop
|
, M. Hashimoto
|
量子ドットとイメージセンサを用いたリザバーコンピューティングによる画像分類
|
電子情報通信学会ソサイエティ大会
|
|
|
September 2023
|
|
|
Workshop
|
, M. Hashimoto
|
ミューオン起因ソフトエラーの物理現象解明に向けた照射実験と解析
|
LSIとシステムのワークショップ
|
|
|
May 2023
|
|
|
Workshop
|
, , , , , , 渡辺幸信, 安部晋一郎, , , , , , , M. Hashimoto
|
12-nm FinFETおよび28-nm プレナー型SRAMのミューオン起因ソフトエラー断面積の評価
|
電子情報通信学会 集積回路研究会
|
|
|
April 2023
|
|
|
Workshop
|
, , M. Hashimoto
|
LPDDR4 SDRAMとGDDR5 SDRAMのソフトエラー耐性の実測評価
|
電子情報通信学会 VLSI設計技術研究会
|
|
|
January 2023
|
|
|
Workshop
|
M. Hashimoto
|
ミュオン起因ソフトエラーの測定と課題
|
日本原子力学会2022年秋の大会
|
|
|
September 2022
|
|
|
Workshop
|
, , M. Hashimoto, 密山幸男
|
仮想環境を用いたSRAM型FPGAにおける ソフトエラー評価手法
|
情報処理学会SLDM研究会
|
|
|
March 2022
|
|
|
Workshop
|
, M. Hashimoto
|
FRETを利用したリザバーコンピューティングの小型デバイス実装の検討
|
電子情報通信学会総合大会講演論文集
|
|
|
March 2022
|
|
|
Workshop
|
, M. Hashimoto
|
モデル抽出攻撃に対して決定木構造漏洩がもたらす危険性評価
|
電子情報通信学会総合大会講演論文集
|
|
|
March 2022
|
|
|
Workshop
|
, M. Hashimoto
|
CNNの組み合わせ回路実装に向けた重み調整によるLUT数削減手法の検討
|
情報処理学会SLDM研究会
|
|
|
January 2022
|
|
|
Workshop
|
, 白井僚, M. Hashimoto
|
小体積IoTノード向け磁界式バックスキャッタ通信手法の提案と評価
|
電子情報通信学会 集積回路研究会
|
|
|
December 2021
|
|
|
Workshop
|
, 白井僚, M. Hashimoto
|
磁性体金属異物に対してロバストな直流磁界を用いた位置推定手法の検討
|
電子情報通信学会 集積回路研究会
|
|
|
December 2021
|
|
|
Workshop
|
白井僚, , , , M. Hashimoto
|
360度視野角を有する3Dディスプレイの実現に向けた，極小画素ドットへの水中無線給電技術
|
電子情報通信学会 集積回路研究会
|
|
|
December 2021
|
|
|
Workshop
|
川瀬頌一郎, 福田 宏哉, 渡辺幸信, 新倉潤, 橋本昌宜
|
半導体デバイスにおける宇宙線ミュオン起因ソフトエラー発生率評価に向けたミュオン原子核捕獲反応測定計画 (1)概要
|
日本原子力学会2021年秋の大会
|
|
|
September 2021
|
|
|
Workshop
|
, Y. Masuda, , , J. Chen, M. Hashimoto
|
Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization
|
電子情報通信学会 VLSI設計技術研究会
|
|
|
March 2021
|
|
|
Workshop
|
, 橋本昌宜
|
ビアスイッチのプログラミング電流制限によるバリスタ破損防止と抵抗値均質化の実験的評価
|
電子情報通信学会総合大会講演論文集
|
|
|
March 2021
|
|
|
Workshop
|
, , 橋本昌宜
|
画素アレイ上の可変抵抗クロスバーを用いた フィルタ演算のエネルギー評価
|
電子情報通信学会総合大会講演論文集
|
|
|
March 2021
|
|
|
Workshop
|
今川隆司, 劉載勲, 橋本昌宜, 越智裕之
|
Via-Switch FPGAを対象とする算術演算アプリケーション回路の実装方式検討
|
電子情報通信学会 VLSI設計技術研究会
|
|
|
March 2020
|
|
|
Workshop
|
井口憲幸, 伴野直樹, 岡本浩一郎, , 橋本昌宜, 杉林直彦, 阪本利司, 多田宗弘
|
積層a-Si/SiN/a-Siバリスタを有するビアスイッチ素子の開発
|
応用物理学会春季学術講演会
|
|
|
February 2020
|
|
|
Workshop
|
白井僚, 橋本昌宜
|
送信機と電源線のインピーダンスを整合させる電源線アンテナ化手法
|
電子情報通信学会 集積回路研究会
|
|
|
December 2019
|
|
|
Workshop
|
橋本昌宜
|
高エネルギー効率コンピューティングを実現するビアスイッチFPGA (Invited)
|
電子情報通信学会VLSI設計技術研究会
|
|
|
May 2019
|
|
|
Workshop
|
|
スパイキングニューラルネットワークの教師あり学習法の検討
|
電子情報通信学会総合大会講演論文集
|
|
|
March 2019
|
|
|
Workshop
|
|
FPGAを用いた動的電源ノイズ下でのエラー予告FFの動作検証
|
電子情報通信学会総合大会講演論文集
|
|
|
March 2019
|
|
|
Workshop
|
清水綾平, 白井僚, 陳沛豪, 橋本昌宜
|
地磁気センサアレイの時系列データを用いた動き予測の検討
|
電子情報通信学会 回路とシステム研究会
|
|
|
December 2018
|
|
|
Workshop
|
白井僚, 陳沛豪, 清水綾平, 橋本昌宜
|
単一アンカーコイルによる直流磁界を用いた位置推定手法の検討
|
電子情報通信学会 回路とシステム研究会
|
|
|
December 2018
|
|
|
Workshop
|
佐藤雅紘, 増田豊, 橋本昌宜
|
過電圧スケーリングを用いた不正確計算による消費電力削減の検討
|
電子情報通信学会VLSI設計技術研究会
| (VLD2017-123)
|
|
March 2018
|
|
|
Workshop
|
中澤祐希, 土井龍太郎, 劉載勲, 橋本昌宜
|
ビアスイッチFPGA向け配線遅延解析手法の検討
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2017-120)
|
|
March 2018
|
|
|
Workshop
|
葛西孝己, 神藤始, 陳俊, 橋本昌宜, 今井雅, 黒川敦, 金本俊幾
|
容量素子最適化のためのLSI・パッケージ・ボード電源網解析モデルの構築
|
情報処理学会東北支部研究報告
|
|
|
February 2018
|
|
|
Workshop
|
白井僚, 廣瀬哲也, 橋本昌宜
|
IoTノード向けアンテナ組込型小体積高効率トランスミッタの開発
|
電子情報通信学会 集積回路研究会
|
|
|
December 2017
|
|
|
Workshop
|
白井僚, 河野仁, 廣瀬哲也, 橋本昌宜
|
近傍界磁界通信・電界測距共用mm3級アンテナの実装と評価
|
電子情報通信学会 回路とシステム研究会
|
|
|
December 2017
|
|
|
Workshop
|
橋本昌宜
|
高エネルギー効率コンピューティングを実現するビアスイッチFPGA の開発 (Invited)
|
電気関連学会関西連合大会
|
|
|
November 2017
|
|
|
Workshop
|
伴野直樹, 多田宗弘, 岡本浩一郎, 井口憲幸, 阪本利司, 波田博光, 越智裕之, 小野寺秀俊, 橋本昌宜, 杉林直彦
|
低電力FPGAを実現するビアスイッチ技術を用いた大規模クロスバースイッチの実証 (Invited)
|
電子情報通信学会シリコン材料・デバイス研究会
| (SDM2016-144)
|
|
February 2017
|
|
|
Workshop
|
橋本昌宜
|
超低電圧SRAMのソフトエラー耐性 (Invited)
|
電子情報通信学会 集積回路研究会
| (ICD2016-22)
|
53--58
|
August 2016
|
|
|
Workshop
|
J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto
|
Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch
|
Work in Progress Session, Design Automation Conference (DAC)
|
|
|
June 2016
|
|
|
Workshop
|
檜原弘樹, 岩崎晃, 橋本昌宜, 越智裕之, 密山幸男, 小野寺秀俊, 神原弘之, 若林一敏, 杉林直彦, 竹中崇, 波田博光, 多田宗弘
|
センサの知能化に適したプロセッサアーキテクチャの考察
|
電子情報通信学会ディペンダブルコンピューティング研究会
| (DC2015-8)
|
43--48
|
April 2015
|
|
|
Workshop
|
S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye
|
Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator
|
電子情報通信学会 VLSI設計技術研究会
|
|
|
March 2015
|
|
|
Workshop
|
佐藤雅紘, 飯塚翔一, 粟野皓光, 橋本昌宜, 尾上孝雄
|
NBTIによる閾値電圧変化の確率的モデル化に関する一考察
|
2015年電子情報通信学会総合大会講演論文集
|
|
|
March 2015
|
|
|
Workshop
|
河野仁, 橋本昌宜, 近藤利彦, 森村浩季
|
超小型コイルを用いた近距離無線通信における周辺コイルの影響評価
|
2015年電子情報通信学会総合大会講演論文集
|
|
|
March 2015
|
|
|
Workshop
|
益田涼平, 橋本昌宜, 尾上孝雄
|
サーモパイル型赤外線センサを用いた人感センサの性能評価
|
2015年電子情報通信学会総合大会講演論文集
|
|
|
March 2015
|
|
|
Workshop
|
鵜川翔平，信田龍哉，橋本昌宜，伊藤雄一，尾上孝雄
|
クロスエントロピー法を用いたノード間距離情報に基づく3次元ノード位置推定
|
情報処理学会ヒューマンコンピュータインタラクション研究会
|
|
|
January 2015
|
|
|
Workshop
|
土井龍太郎, 橋本昌宜, 尾上孝雄
|
時間的三重化によるソフトエラー耐性向上の解析的評価
|
電子情報通信学会ディペンダブルコンピューティング研究会
|
|
|
November 2014
|
|
|
Workshop
|
M. Hashimoto, M. Ueno, T. Onoye
|
Real-Time Supply Voltage Sensor for Trace-Based Fault Localization
|
Poster Session, International Test Conference (ITC)
|
|
|
October 2014
|
|
|
Workshop
|
河野仁, 鵜川翔平, 信田龍哉, 塚元瑞穂, 田中勇気, 中島康祐, 伊藤雄一, 廣瀬哲也, 橋本昌宜
|
リアルタイム3次元モデリングシステムiClayの実現に向けた1mm^3級センサノードの要素技術開発
|
LSIとシステムのワークショップ
|
|
|
May 2014
|
|
|
Workshop
|
飯塚翔一, 水野雅文, 黒田弾, 橋本昌宜, 尾上孝雄
|
プロセッサの適応的速度制御における故障発生時間見積り高速化に関する研究
|
LSIとシステムのワークショップ
|
|
|
May 2014
|
|
|
Workshop
|
鵜川翔平, 信田龍哉, 伊藤雄一, 橋本昌宜, 尾上孝雄
|
ノード間距離情報に基づいた逐次的3次元ノード位置推定手法の検討
|
電子情報通信学会 回路とシステム研究会
| (CAS2012-119)
|
131--136
|
March 2014
|
|
|
Workshop
|
郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄
|
動的部分再構成による故障回避に適した初期配置配線の検討
|
情報処理学会SLDM研究会
|
|
|
March 2014
|
|
|
Workshop
|
橋本昌宜
|
オンチップばらつきモニタリングによる適応的性能補償 (Invited)
|
電子情報通信学会 集積回路研究会
| (IEICE-ICD2013-100)
|
|
January 2014
|
|
|
Workshop
|
尾上孝雄, 橋本昌宜, 密山幸男, Dawood Alnajjar, 郡浦宏明
|
VLSIの信頼性を向上させる再構成可能アーキテクチャ (Invited)
|
電子情報通信学会リコンフィギャラブルシステム研究会
| (IEICE-RECONF2013-51)
|
|
November 2013
|
|
|
Workshop
|
M. Hashimoto
|
Reliability Challenge for Exa-Scale Near-Threshold Computing -- Soft Error Perspective --
|
Elevator Talk Session, International Test Conference (ITC)
|
|
|
September 2013
|
|
|
Workshop
|
作田賢志朗, 安部晋一郎, 渡辺幸信, 原田諒, 橋本昌宜, 更田裕司, 上村大樹
|
宇宙線中性子起因マルチセルアップセットのスケーリング則調査
|
応用物理学会秋期学術講演会
|
|
|
September 2013
|
|
|
Workshop
|
郡浦宏明, Dawood Alnajjar, 密山幸男, 越智裕之, 今川隆司, 野田真一, 若林一敏, 橋本昌宜, 尾上孝雄
|
動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討
|
電子情報通信学会リコンフィギャラブルシステム研究会
| (RECONF2013-8 )
|
41--46
|
May 2013
|
|
|
Workshop
|
原田諒, 密山幸男, 橋本昌宜, 尾上孝雄
|
放射線起因一過性パルスが信頼性に与える影響の実験的評価
|
LSI とシステムのワークショップ
|
|
|
May 2013
|
|
|
Workshop
|
郡浦宏明, Dawood Alnajjar, 密山幸男, 越智裕之, 今川隆司, 野田真一, 若林一敏, 橋本昌宜, 尾上孝雄
|
C ベース設計に対応した信頼性可変粒度複合型再構成可能アーキテクチャ
|
LSIとシステムのワークショップ
|
|
|
May 2013
|
|
|
Workshop
|
天木健彦, 橋本昌宜, 密山幸男, 尾上孝雄
|
確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2012-154)
|
99--104
|
March 2013
|
|
|
Workshop
|
樋口裕磨, 橋本昌宜, 尾上孝雄
|
オンチップセンサを用いたばらつき自己補償手法の検討
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2012-138)
|
13--17
|
March 2013
|
|
|
Workshop
|
信田龍哉, 橋本昌宜, 尾上孝雄
|
センサノード間静電容量結合に基づく距離推定に向けた電極形状の検討
|
電子情報通信学会 回路とシステム研究会
| (CAS2012-119)
|
131--136
|
March 2013
|
|
|
Workshop
|
原田諒, 密山幸男, 橋本昌宜, 尾上孝雄
|
中性子起因一過性複数パルスの電源電圧及び基板バイアス依存性測定
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2012-100)
|
237--241
|
November 2012
|
|
|
Workshop
|
郡浦宏明, 今川隆司, 密山幸男, 橋本昌宜, 尾上孝雄
|
動的再構成機能を用いた故障回避手法の定量的信頼性評価
|
電子情報通信学会 リコンフィギャラブルシステム研究会
| (RECONF2012-59)
|
71--76
|
November 2012
|
|
|
Workshop
|
M. Hashimoto
|
Adaptive Speed Control and Its Extremely-Low Error Rate Estimation
|
Elevator Talk Session, International Test Conference (ITC)
|
|
|
November 2012
|
|
|
Workshop
|
上野美保, 橋本昌宜, 尾上孝雄
|
電気的タイミング故障のデバッグ向けオンチップリアルタイム電源電圧センサ
|
2012年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-6)
|
|
September 2012
|
|
|
Workshop
|
安部晋一郎, 渡辺幸信, 原田諒, 橋本昌宜, 更田裕司, 上村大樹
|
宇宙線中性子起因ソフトエラーに関するマルチセルアップセット解析
|
応用物理学会秋期学術講演会
|
|
|
September 2012
|
|
|
Workshop
|
天木健彦, 橋本昌宜, 尾上孝雄
|
ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器
|
電子情報通信学会 集積回路研究会
| (ICD2011-118)
|
87--92
|
December 2011
|
|
|
Workshop
|
I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye
|
Signal-Dependent Analog-To-Digital Conversion Based on Minimax
|
電子情報通信学会 集積回路研究会
| ( ICD2011-121)
|
105--107
|
December 2011
|
|
|
Workshop
|
橋本昌宜
|
超低電圧サブスレショルド回路設計
|
電子情報通信学会 VLSI設計技術研究会
| (VLD211-82)
|
173--178
|
November 2011
|
|
|
Workshop
|
橋本昌宜
|
超低電圧SRAMにおける中性子起因ソフトエラーの評価
|
ソフトエラー(などのLSIにおける放射線効果)に関する第1回勉強会
|
|
|
September 2011
|
|
|
Workshop
|
郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄
|
動的再構成可能アーキテクチャによる故障回避機構の定量的信頼性評価
|
電子情報通信学会 リコンフィギャラブルシステム研究会
| (RECONF2011-6)
|
31--36
|
May 2011
|
|
|
Workshop
|
橋本昌宜, 更田裕司
|
超低電圧サブスレショルド回路設計
|
2011年電子情報通信学会総合大会講演論文集
|
|
|
March 2011
|
|
|
Workshop
|
高井康充, 橋本昌宜, 尾上孝雄
|
電源ノイズに注目した電源遮断法の実機評価
|
電子情報通信学会 集積回路研究会
| (ICD2010-109)
|
75-80
|
December 2010
|
|
|
Workshop
|
橋本昌宜
|
国際会議への論文の執筆ガイド 〜 VLSI設計技術分野での一考察 〜
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2010-69)
|
91
|
November 2010
|
|
|
Workshop
|
天木健彦, 橋本昌宜, 密山幸男, 尾上孝雄
|
確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法
|
情報処理学会システムLSI設計技術研究会
|
|
|
November 2010
|
|
|
Workshop
|
原田諒, 密山幸男, 橋本昌宜, 尾上孝雄
|
高時間分解能を実現するSETパルス幅測定回路の提案
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2010-55)
|
77--82
|
September 2010
|
|
|
Workshop
|
橋本昌宜
|
製造・環境ばらつきを考慮した統計的静的タイミング解析
|
エレクトロニクス実装学会 システムJisso-CAD/CAE研究会公開研究会
|
|
|
June 2010
|
|
|
Workshop
|
原田諒, 更田裕司, 密山幸男, 橋本昌宜, 尾上孝雄
|
α線起因ソフトエラー測定 -SETパルス幅測定回路の提案および超低電圧SRAMのSEU耐性評価-
|
LSIとシステムのワークショップ
|
|
212--214
|
May 2010
|
|
|
Workshop
|
郡浦宏明, D. Alnajjar, 高永勲, 今川隆司, 廣本正之, 密山幸男, 橋本昌宜, 越智裕之, 尾上孝雄
|
柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャ
|
LSIとシステムのワークショップ
|
|
191--193
|
May 2010
|
|
|
Workshop
|
橋本昌宜, 更田裕司, 尾上孝雄
|
製造ばらつきや環境変動を許容するサブスレッショルド回路設計
|
2010年電子情報通信学会総合大会講演論文集
| (AS-1-4)
|
|
March 2010
|
|
|
Workshop
|
黒田弾, 更田裕司, 橋本昌宜, 尾上孝雄
|
低消費エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価
|
情報処理学会SLDM研究会
| 2009-SLDM-141(19)
|
|
October 2009
|
|
|
Workshop
|
榎並孝司, 新開健一, 二宮進有, 阿部慎也, 橋本昌宜
|
製造ばらつき、電源変動を統一的に取り扱った統計的静的タイミング解析手法
|
LSIとシステムのワークショップ
|
|
283--285
|
May 2009
|
|
|
Workshop
|
榎並孝司, 橋本昌宜, 佐藤高史
|
電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2008-161)
|
|
March 2009
|
|
|
Workshop
|
更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
|
サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2008-160)
|
|
March 2009
|
|
|
Workshop
|
濱本浩一, 橋本昌宜, 密山幸男, 尾上孝雄
|
レイアウトを考慮した基板バイアスクラスタリング手法
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2008-159)
|
|
March 2009
|
|
|
Workshop
|
高永勲, Dawood Alnajjar, 密山幸男, 橋本昌宜, 尾上孝雄
|
柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャの検討
|
電子情報通信学会ディペンダブルコンピューティング研究会
| (DC2008-41)
|
|
November 2008
|
|
|
Workshop
|
濱本浩一, 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
|
基板バイアス印加レイアウト方式の面積効率と速度制御性の評価
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2008-14)
|
|
June 2008
|
|
|
Workshop
|
鉢田卓也, 松中栄貴, 白川功, 築山修治, 橋本昌宜
|
nMOSダイナミック論理を用いた液晶駆動回路の設計手法
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2007-148)
|
|
March 2008
|
|
|
Workshop
|
小笠原泰弘, 橋本昌宜, 尾上孝雄
|
バス配線における誘導性クロストークノイズによる遅延変動の実測とノイズ重ね合わせ効果の検証
|
電子情報通信学会 集積回路研究会
| (ICD2007-176)
|
|
March 2008
|
|
|
Workshop
|
大津誠, 高橋真吾, 築山修治, 橋本昌宜, 白川功
|
nMOSレベルシフタ回路の性能比較手法について
|
情報処理学会システムLSI設計技術研究会
| (2008-SLDM-134)
|
121--126
|
March 2008
|
|
|
Workshop
|
渡辺慎吾, 橋本昌宜, 佐藤寿倫
|
性能歩留まり改善を目的とする演算器カスケーディングの提案
|
第14回「ハイパフォーマンスコンピューティングとアーキテクチャの評価」に関する北海道ワークショップ（HOKKE-2008）
| (2007-ARC-177 )
|
43--48
|
March 2008
|
| 103.pdf
|
Workshop
|
小笠原泰弘, 橋本昌宜, 尾上孝雄
|
スタンダードセルで構成された電源ノイズ波形測定回路の提案
|
電子情報通信学会 集積回路研究会
| (CPM2007-131, ICD2007-142)
|
17--22
|
January 2008
|
|
|
Workshop
|
二宮進有, 橋本昌宜
|
SSTAにおける空間的相関を持つ製造ばらつきのグリッドベースモデル化法の検討
|
電子情報通信学会VLSI設計技術研究会
| (VLD2007-91,DC2007-45)
|
13--17
|
November 2007
|
|
|
Workshop
|
橋本昌宜
|
オンチップノイズ観測
|
第11回システムLSIワークショップ
|
|
149--157
|
November 2007
|
|
|
Workshop
|
橋本昌宜
|
製造・環境ばらつきを考慮したタイミング検証技術
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2007-65)
|
21--24
|
October 2007
|
|
|
Workshop
|
榎並孝司, 橋本昌宜
|
統計的電源ノイズモデル化に適した適応的領域分割法
|
2007年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-10)
|
|
September 2007
|
| 93.pdf
|
Workshop
|
高橋真吾，築山修治，橋本昌宜，白川功
|
液晶ディスプレイ用サンプリング回路の最適性について
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2006-144)
|
|
March 2007
|
|
|
Workshop
|
Siriporn Jangsombatsiri, 橋本昌宜, 土谷亮, Haikun Zhu, Chun-Kuan Cheng
|
シャントコンダクタンスを挿入したオンチップ伝送線路のアイパターン評価
|
2007年電子情報通信学会総合大会講演論文集
| (A-3-9)
|
|
March 2007
|
| 68.pdf
|
Workshop
|
濱本浩一, 橋本昌宜, 密山幸男, 尾上孝雄
|
低電圧回路向け基板電位制御レイアウト方式の面積効率評価
|
2007年電子情報通信学会総合大会講演論文集
| (A-3-6)
|
|
March 2007
|
| 71.pdf
|
Workshop
|
阿部慎也, 橋本昌宜, 尾上孝雄
|
メッシュ型クロック分配網のスキュー評価
|
2007年電子情報通信学会総合大会講演論文集
| (A-3-5)
|
|
March 2007
|
| 70.pdf
|
Workshop
|
更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
|
加算器を用いたsubthreshold 回路の設計指針の検討
|
2007年電子情報通信学会総合大会講演論文集
| (A-3-17)
|
|
March 2007
|
| 69.pdf
|
Workshop
|
二宮進有, 橋本昌宜
|
空間的相関を考慮したSSTAにおける領域の分割数と精度
|
2007年電子情報通信学会総合大会講演論文集
| (A-3-1)
|
|
March 2007
|
| 67.pdf
|
Workshop
|
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato
|
電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現
|
電子情報通信学会 集積回路研究会,
| (ICD2006-174)
|
|
January 2007
|
|
|
Workshop
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測
|
電子情報通信学会 集積回路研究会
| (ICD2006-173)
|
|
January 2007
|
|
|
Workshop
|
Jangsombatsiri Siriporn, M. Hashimoto, T. Onoye
|
シャントコンダクタンスを挿入したオンチップ伝送線路特性評価
|
第十回シリコンアナログRF研究会
|
|
|
November 2006
|
|
|
Workshop
|
Y. Ogasahara, K. Shinkai, T. Enami, S. Abe, S. Ninomiya, M. Hashimoto
|
ナノメートル世代のVLSIタイミング設計技術の研究
|
第10回システムLSIワークショップ
|
|
195-198
|
November 2006
|
|
|
Workshop
|
K. Shinkai, M. Hashimoto, T. Onoye
|
短距離ブロック内配線の自己発熱問題の将来予測
|
2006年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-14)
|
|
September 2006
|
| 72.pdf
|
Workshop
|
T. Ijichi, M. Hashimoto
|
画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2005-131)
|
|
March 2006
|
|
|
Workshop
|
S. Uemura, A. Tsuchiya, M. Hashimoto, H. Onodera
|
ロードマップに準拠したSPICEトランジスタモデルの構築
|
2006年電子情報通信学会総合大会講演論文集
| (A-3-16)
|
|
March 2006
|
| 76.pdf
|
Workshop
|
T. Enami, M. Hashimoto, T. Onoye
|
電源ノイズ解析のための回路動作部表現法の評価
|
2006年電子情報通信学会総合大会講演論文集
| (A-3-15)
|
|
March 2006
|
| 77.pdf
|
Workshop
|
A. Tsuchiya, A. Shinmyo, M. Hashimoto
|
CMLを用いたオンチップ長距離高速信号伝送技術の開発
|
第9回システムLSIワークショップ
|
|
275-278
|
November 2005
|
|
|
Workshop
|
S. Uemura, M. Hashimoto, H. Onodera
|
LC共振器におけるMOSFETの抵抗成分を考慮した等価並列抵抗の見積もり
|
2005年電子情報通信学会ソサイエティ大会講演論文集
| (C-12-39)
|
|
September 2005
|
| 79.pdf
|
Workshop
|
S. Takahashi
|
液晶ディスプレイ用サンプリング回路の設計手法について
|
2005年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-4)
|
|
September 2005
|
| 78.pdf
|
Workshop
|
Y. Ogasahara, M. Hashimoto, T. Onoye
|
誘導性・容量性クロストークノイズによる遅延変動の測定と評価
|
電子情報通信学会 集積回路研究会
| (ICD2005-74)
|
|
August 2005
|
|
|
Workshop
|
S. Uemura, M. Hashimoto, H. Onodera
|
SOIの基板抵抗率がLNAの性能に及ぼす影響の評価
|
第四回シリコンアナログRF研究会
|
|
|
May 2005
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
オンチップ高速信号伝送用配線の解析的性能評価
|
電子情報通信学会 VLSI設計技術研究会
| (VLD2004-145)
|
|
March 2005
|
|
|
Workshop
|
S. Takahashi
|
液晶ディスプレイ用サンプリングスイッチの一設計法
|
エレクトロニクス実装学術講演大会
| (16B-12)
|
|
March 2005
|
|
|
Workshop
|
S. Uemura, M. Hashimoto, H. Onodera
|
LC型VCO最大発振周波数の実験的検討
|
第三回シリコンアナログRF研究会
|
|
|
January 2005
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
実測と電磁界解析による基板損失の評価
|
第三回シリコンアナログRF研究会
|
|
|
January 2005
|
|
|
Workshop
|
Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa
|
システム液晶設計のための配線容量抽出手法
|
電子情報通信学会 VLSI設計技術研究会(デザインガイア)
| (VLD2004-64)
|
|
December 2004
|
|
|
Workshop
|
M. Hashimoto
|
ナノメートル世代のタイミング解析 -- 信号線・電源線ノイズ、ばらつき、熱への対応 --
|
第8回システムLSIワークショップ
|
|
191-200
|
November 2004
|
|
|
Workshop
|
Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, I. Shirakawa
|
システム液晶に適した配線間容量抽出の検討
|
2004年電子情報通信学会ソサイエティ大会講演論文集
| (A-1-16)
|
|
September 2004
|
|
|
Workshop
|
M. Hashimoto, H. Onodera
|
微細LSIにおけるタイミング解析 --電源ノイズ・信号線ノイズ・ばらつきへの対応--
|
2004年電子情報通信学会ソサイエティ大会講演論文集
|
|
|
September 2004
|
|
|
Workshop
|
S. Uemura, M. Hashimoto, H. Onodera
|
高周波CMOSデバイスモデルを用いたLCVCOの特性見積もりと実測
|
第二回シリコンアナログRF研究会
|
|
|
August 2004
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
基板および周辺信号配線が配線特性に及ぼす影響の実測
|
第二回シリコンアナログRF研究会
|
|
|
August 2004
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響
|
第一回シリコンアナログRF研究会
|
|
|
April 2004
|
|
|
Workshop
|
J. Yamaguchi, M. Hashimoto, H. Onodera
|
ゲート毎の電源電圧変動を考慮した静的遅延解析法
|
電子情報通信学会 VLSI設計技術研究会
| (ICD2003-236/VLD2003-143)
|
|
March 2004
|
|
|
Workshop
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
電源電圧変動に対するオンチップ配線インダクタンスの影響
|
2004年電子情報通信学会総合大会講演論文集
| (A-3-22)
|
|
March 2004
|
|
|
Workshop
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
電源配線の等価回路簡略化による電源解析高速化の検討
|
平成15年度情報処理学会関西支部支部大会 VLSI研究会
| (C-01)
|
169-172
|
November 2003
|
|
|
Workshop
|
T. Miyazaki, M. Hashimoto, H. Onodera
|
デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測 ーLC発振型VCOを用いたPLLの有効性ー
|
電子情報通信学会集積回路研究会
| (ICD2003-99)
|
29-34
|
September 2003
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
オンチップ高速信号配線における波形歪みの影響
|
2003年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-6)
|
56
|
September 2003
|
|
|
Workshop
|
T. Miyazaki, A. Shinmyo, M. Hashimoto, H. Onodera
|
オンチップオシロ用サンプルホールド回路の広周波数帯域化
|
2003年電子情報通信学会総合大会講演論文集
| (C-12-34)
|
103
|
March 2003
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
信号配線と下層配線との結合に対する直交配線の影響
|
2003年電子情報通信学会総合大会講演論文集
| (A-3-14)
|
81
|
March 2003
|
|
|
Workshop
|
A. Muramatsu, M. Hashimoto, H. Onodera
|
オンチップデカップリング容量の最適寄生抵抗値の決定法
|
2003年電子情報通信学会総合大会講演論文集
| (A-3-13)
|
80
|
March 2003
|
|
|
Workshop
|
M. Hashimoto
|
LSI物理設計におけるSignal Integrity問題
|
情報処理学会関西支部VLSIシステム研究会平成14年度第3回研究会
|
|
|
March 2003
|
|
|
Workshop
|
Y. Yamada, M. Hashimoto, H. Onodera
|
静的遅延解析のための等価ゲート入力波形導出法 --VDSMプロセスに起因する波形歪みへの対応--
|
情報処理学会システムLSI設計技術研究会
| (2003-SLDM-108-20)
|
111-116
|
January 2003
|
|
|
Workshop
|
Y. Yamada, M. Hashimoto, H. Onodera
|
容量性クロストークを考慮した高精度タイミング解析に関する研究
|
平成14年度情報処理学会関西支部支部大会 VLSI研究会
| (C-3)
|
113-114
|
November 2002
|
|
|
Workshop
|
T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, A. Ikeuchi, H. Kobayashi, M. Hashimoto
|
インダクタンスに起因する配線遅延変動の統計的予測手法
|
2002年電子情報通信学会ソサイエティ大会講演論文集
| (TA-2-4)
|
247-248
|
September 2002
|
|
|
Workshop
|
M. Hashimoto
|
京大版スタンダードセルライブラリ
|
VDEC LSI デザイナーフォーラム 2002
|
|
|
September 2002
|
|
|
Workshop
|
K. Fujimori, M. Hashimoto, H. Onodera
|
駆動力可変セルレイアウト生成システムによるスタンダードセルライブラリ開発
|
電子情報通信学会VLSI設計技術研究会
| (VLD2001-147/ICD2001-222)
|
|
March 2002
|
|
|
Workshop
|
Y. Yamada, M. Hashimoto, H. Onodera
|
ゲート出力波形導出時の誤差要因とその影響の評価
|
2002年電子情報通信学会総合大会講演論文集
| (A-3-3)
|
82
|
March 2002
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
LSI配線インダクタンスに対する直交配線の影響
|
2002年電子情報通信学会総合大会講演論文集
| (A-3-23)
|
102
|
March 2002
|
|
|
Workshop
|
M. Hashimoto, M. Takahashi, H. Onodera
|
ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法
|
情報処理学会システムLSI設計技術研究会(デザインガイア)
| (SLDM103-6)
|
39-44
|
November 2001
|
|
|
Workshop
|
M. Takahashi, M. Hashimoto, H. Onodera
|
波形重ね合せによるクロストーク遅延変動量の見積もり手法
|
2001年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-9)
|
63
|
September 2001
|
|
|
Workshop
|
M. Hashimoto, M. Takahashi, H. Onodera
|
ポストレイアウトトランジスタ寸法最適化によるクロストークノイズ削減手法
|
2001年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-8)
|
62
|
September 2001
|
|
|
Workshop
|
A. Tsuchiya, M. Hashimoto, H. Onodera
|
長距離高速配線における RC モデルに基づく回路設計の限界
|
2001年電子情報通信学会ソサイエティ大会講演論文集
| (A-3-6)
|
60
|
September 2001
|
|
|
Workshop
|
M. Hashimoto, M. Takahashi, H. Onodera
|
隣接位置を考慮した解析的クロストークノイズモデル ---実回路への 適用---
|
2001年電子情報通信学会総合大会講演論文集
| (A-3-6)
|
84
|
March 2001
|
|
|
Workshop
|
M. Takahashi, M. Hashimoto, H. Onodera
|
隣接位置を考慮した解析的クロストークノイズモデル ---導出と評価 ---
|
2001年電子情報通信学会総合大会講演論文集
| (A-3-5)
|
83
|
March 2001
|
|
|
Workshop
|
M. Hashimoto, H. Onodera
|
パスバランス回路における遅延不確かさの統計的解析
|
電子情報通信学会VLSI設計技術研究会(デザインガイア)
| (VLD2000-72)
|
|
November 2000
|
|
|
Workshop
|
M. Hashimoto, H. Onodera
|
パスバランス回路における遅延不確かさの統計的解析
|
2000年電子情報通信学会基礎・境界ソサイエティ大会講演論文集
| (A-3-9)
|
76
|
September 2000
|
|
|
Workshop
|
M. Hashimoto
|
オンデマンドライブラリを用いた最適LSI設計手法
|
VDEC LSI デザイナーフォーラム
|
|
|
August 2000
|
|
|
Workshop
|
M. Hashimoto, T. Hashimoto, R. Nishikawa, D. Fukuda, S. Kuroda, S. Suga, H. Kanbara, H. Onodera
|
オンデマンドライブラリを用いたシステムLSI詳細設計手法
|
電子情報通信学会VLSI設計技術研究会
| (VLD99-112/ICD99-269)
|
|
March 2000
|
|
|
Workshop
|
M. Hashimoto, H. Onodera
|
静的統計遅延解析を用いた最悪遅延時間計算手法
|
2000年電子情報通信学会総合大会講演論文集
| (A-3-13)
|
81
|
March 2000
|
|
|
Workshop
|
M. Hashimoto, T. Hashimoto
|
オンデマンドライブラリを用いたシステムLSI詳細設計手法
|
第3回 システムLSI琵琶湖ワークショップ
|
|
279-281
|
November 1999
|
|
|
Workshop
|
M. Hashimoto, H. Onodera
|
スタンダードセルライブラリの駆動能力種類の追加による消費電力削減効果の検討
|
1999年電子情報通信学会基礎・境界ソサイエティ大会講演論文集
| (A-3-9)
|
52
|
September 1999
|
|
|
Workshop
|
M. Hashimoto, H. Onodera, K. Tamaru
|
グリッチの削減を考慮したゲート寸法最適化による消費電力削減手法 ---レイアウト設計への適用---
|
1998年電子情報通信学会基礎・境界ソサイエティ大会講演論文集
| (A-3-5)
|
|
September 1998
|
|
|
Workshop
|
M. Hashimoto, H. Onodera, K. Tamaru
|
論理シミュレーションを用いた消費電力見積もりの高精度化手法
|
1998年電子情報通信学会総合大会講演論文集
| (A-3-5)
|
91
|
March 1998
|
|
|
Workshop
|
M. Hashimoto, H. Onodera, K. Tamaru
|
入力端子接続最適化による遅延時間と消費電力の最適化手法
|
1997年電子情報通信学会基礎・境界ソサイエティ大会講演論文集
| (A-3-15)
|
67
|
September 1997
|
|
|
Book
|
|
Photonic Neural Networks with Spatiotemporal Dynamics
|
Springer Singapore
|
|
|
October 2023
|
|
|
Book
|
H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto
|
Atomic Switch FPGA: Application for IoT Sensing Systems in Space
|
Book Chapter, Atomic Switch, Springer
|
|
|
March 2020
|
|
|
Book
|
, , , , K. Kobayashi, , Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera
|
Radiation-Induced Soft Errors
|
Book chapter, VLSI Design and Test for Systems Dependability, Springer
|
|
|
August 2018
|
|
|
Book
|
H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada
|
Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space
|
Book chapter, VLSI Design and Test for Systems Dependability, Springer
|
|
|
August 2018
|
|
|
Book
|
T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao
|
Time-Dependent Degradation in Device Characteristics and Countermeasures by Design
|
Book chapter, VLSI Design and Test for Systems Dependability, Springer
|
|
|
August 2018
|
|
|
Book
|
M. Hashimoto, R. Nair
|
Power Integrity for Nanoscale Integrated Systems
|
McGraw-Hill Professional
|
|
|
February 2014
|
|
|
Book
|
M. Hashimoto, R. Nair
|
Power Integrity Management in Integrated Circuits and Systems
|
Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR
|
|
|
May 2010
|
|
|
Book
|
R. Nair, M. Hashimoto, N. Srivastava
|
IC Power Integrity and Optimal Power Delivery
|
Book chapter, Power Integrity Analysis and Management for Integrated Circuits, Prentice Hall PTR
|
|
|
May 2010
|
|
|
Article
|
M. Hashimoto
|
環境放射線と半導体デバイスのソフトエラー ミューオン起因ソフトエラーの測定と課題
|
日本原子力学会誌ATOMOΣ
| 65(5)
|
323-325
|
May 2023
|
|
|
Article
|
橋本昌宜
|
宇宙線ミューオンが電子機器の誤作動を引き起こす
|
Isotope News
| (761)
|
|
February 2019
|
| pdf
|
Article
|
佐藤高史, 橋本昌宜
|
経時劣化概説
|
信頼性学会誌
| 35(8)
|
457--458
|
December 2013
|
|
|
Article
|
橋本昌宜
|
超低電力サブスレッショルド回路設計技術
|
IEICE Fundamentals Review
|
|
30--37
|
July 2013
|
| 189.pdf
|
Article
|
橋本昌宜
|
遅延ばらつきを考慮したVLSIタイミング検証
|
エレクトロニクス実装学会誌
| 11(3)
|
182--185
|
May 2008
|
|
|
