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BibTeX list of works

20 件の該当がありました． : このページのURL : HTML

@article{id514,
         title = {A {Multi-Core} Chip Load Model for {PDN} Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions},
        author = {J. Chen and H. Kando and T. Kanamoto and C. Zhuo and M. Hashimoto},
       journal = {IEEE Transactions on Components, Packaging and Manufacturing Technology},
        volume = {9},
        number = {9},
         pages = {1669--1679},
         month = {9},
          year = {2019},
}

@article{id317,
         title = {Supply Noise Suppression by Triple-Well Structure},
        author = {Y. Ogasahara and M. Hashimoto and T. Kanamoto and T. Onoye},
       journal = {IEEE Transactions on VLSI Systems},
        volume = {21},
        number = {4},
         pages = {781--785},
         month = {4},
          year = {2013},
}

@article{id257,
         title = {Impact of Self-heating in Wire Interconnection on Timing},
        author = {T. Kanamoto and T. Okumura and K. Furukawa and H. Takafuji and A. Kurokawa and K. Hachiya and T. Sakata and M. Tanaka and H. Nakashima and H. Masuda and T. Sato and M. Hashimoto},
       journal = {IEICE Trans. on Electronics},
        volume = {E93-C},
        number = {3},
         pages = {388--392},
         month = {3},
          year = {2010},
}

@article{id251,
         title = {An Approach for Reducing Leakage Current Variation due to Manufacturing Variability},
        author = {T. Sakata and T. Okumura and A. Kurokawa and H. Nakashima and H. Masuda and T. Sato and M. Hashimoto and K. Hachiya and K. Furukawa and M. Tanaka and H. Takafuji and T. Kanamoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E92-A},
        number = {12},
         pages = {3016--3023},
         month = {12},
          year = {2009},
}

@article{id246,
         title = {Interconnect Modeling: A Physical Design Perspective (Invited)},
        author = {A. Kurokawa and T. Sato and T. Kanamoto and M. Hashimoto},
       journal = {IEEE Transactions on Electron Devices},
        volume = {56},
        number = {9},
         pages = {1840--1851},
         month = {9},
          year = {2009},
}

@article{id230,
         title = {Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations},
        author = {T. Okumura and A. Kurokawa and H. Masuda and T. Kanamoto and M. Hashimoto and H. Takafuji and H. Nakashima and N. Ono and T. Sakata and T. Sato},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {92-A},
        number = {4},
         pages = {990--997},
         month = {4},
          year = {2009},
}

@article{id214,
         title = {Impact of Well Edge Proximity Effect on Timing},
        author = {T. Kanamoto and Y. Ogasahara and K. Natsume and K. Yamaguchi and H. Amishiro and T. Watanabe and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E91-A},
        number = {12},
         pages = {3461-3464},
         month = {12},
          year = {2008},
}

@article{id5,
         title = {Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in {SoC} Design},
        author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E89-A},
        number = {12},
         pages = {3560-3568},
         month = {12},
          year = {2006},
}

@article{id7,
         title = {Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation },
        author = {T. Kanamoto and S. Akutsu and T. Nakabayashi and T. Ichinomiya and K. Hachiya and A. Kurokawa and H. Ishikawa and S. Muromoto and H. Kobayashi and  M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E89-A},
        number = {12},
         pages = {3666-3670},
         month = {12},
          year = {2006},
}

@article{id22,
         title = {遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法},
        author = {金本俊幾 and 佐藤高史 and 黒川敦 and 川上善之 and 岡宏規 and 北浦智靖 and 小林宏行 and 橋本昌宜},
       journal = {情報処理学会論文誌},
        volume = {44},
        number = {5},
         pages = {1301-1310},
         month = {5},
          year = {2003},
}

@article{id475,
         title = {An On-Chip Load Model for Off-Chip {PDN} Analysis Considering Interdependency Between Supply Voltage, Current Profile and Clock Latency},
        author = {J. Chen and T. Kanamoto and H. Kando and M. Hashimoto},
       journal = {Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)},
         month = {5},
          year = {2018},
}

@article{id217,
         title = {Measurement of Supply Noise Suppression by Substrate and Deep N-well in 90nm Process},
        author = {Y. Ogasahara and M. Hashimoto and T. Kanamoto and T. Onoye},
       journal = {Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)},
         pages = {397--400},
         month = {11},
          year = {2008},
}

@article{id182,
         title = {Impact of Well Edge Proximity Effect on Timing},
        author = {T. Kanamoto and Y. Ogasahara and K. Natsume and K. Yamaguchi and H. Amishiro and T. Watanabe and M. Hashimoto},
       journal = {Proceedings of 37th European Solid-State Device Research Conference (ESSDERC)},
         pages = {115--118},
         month = {9},
          year = {2007},
}

@inproceedings{id35,
         title = {Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in {SoC} Design},
        author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto},
     booktitle = {Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)},
         pages = {227-230},
         month = {5},
          year = {2006},
}

@inproceedings{id38,
         title = {Effective Si-substrate Modeling for Frequency-dependent Interconnect Resistance and Inductance Extraction},
        author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M. Hashimoto},
     booktitle = {Proceedings of International Workshop on Compact Modeling (IWCM)},
         pages = {51-56},
         month = {1},
          year = {2006},
}

@inproceedings{id72,
         title = {Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay using Electrical and Physical Parameters},
        author = {T. Sato and T. Kanamoto and A. Kurokawa and Y. Kawakami and H. Oka and T. Kitaura and H. Kobayashi and M. Hashimoto},
     booktitle = {Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)},
         pages = {149-155},
         month = {1},
          year = {2003},
}

@inproceedings{id122,
         title = {遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価},
        author = {金本 俊幾 and 阿久津滋聖 and 中林 太美世 and 一宮 敬弘 and 蜂屋 孝太郎 and 石川 博 and 室本 栄 and 小林 宏行 and 橋本 昌宜 and 黒川 敦},
     booktitle = {情報処理学会DAシンポジウム},
         pages = {265-270},
         month = {7},
          year = {2004},
}

@inproceedings{id141,
         title = {0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法},
        author = {金本 俊幾 and 佐藤 高史 and 黒川 敦 and 川上 善之 and 岡 宏規 and 北浦 智靖 and 池内 敦彦 and 小林 宏行 and 橋本 昌宜},
     booktitle = {情報処理学会DAシンポジウム},
         pages = {149-154},
         month = {7},
          year = {2002},
}

@inproceedings{id144,
         title = {インダクタンスが配線遅延に及ぼす影響の定量的評価方法},
        author = {佐藤高史 and 金本俊幾 and 黒川敦 and 川上善之 and 岡宏規 and 北浦智靖 and 池内敦彦 and 小林宏行 and 橋本昌宜},
     booktitle = {第15回 回路とシステム(軽井沢)ワークショップ},
         pages = {493-498},
         month = {4},
          year = {2002},
}

@inproceedings{id139,
         title = {インダクタンスに起因する配線遅延変動の統計的予測手法},
        author = {佐藤高史 and 金本俊幾 and 黒川敦 and 川上善之 and 岡宏規 and 北浦智靖 and 池内敦彦 and 小林宏行 and 橋本昌宜},
     booktitle = {2002年電子情報通信学会ソサイエティ大会講演論文集},
        number = {TA-2-4},
         pages = {247-248},
         month = {9},
          year = {2002},
}