Academic Journal
|
J. Chen, H. Kando, T. Kanamoto, , M. Hashimoto
|
A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions
|
IEEE Transactions on Components, Packaging and Manufacturing Technology
| 9(9)
|
1669--1679
|
September 2019
|
| pdf
|
Academic Journal
|
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
|
Supply Noise Suppression by Triple-Well Structure
|
IEEE Transactions on VLSI Systems
| 21(4)
|
781--785
|
April 2013
|
| 169.pdf
|
Academic Journal
|
T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto
|
Impact of Self-Heating in Wire Interconnection on Timing
|
IEICE Trans. on Electronics
| E93-C(3)
|
388--392
|
March 2010
|
| 136.pdf
|
Academic Journal
|
T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto
|
An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E92-A(12)
|
3016--3023
|
December 2009
|
| 129.pdf
|
Academic Journal
|
A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto
|
Interconnect Modeling: a Physical Design Perspective (Invited)
|
IEEE Transactions on Electron Devices
| 56(9)
|
1840--1851
|
September 2009
|
| 126.pdf
|
Academic Journal
|
T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato
|
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| 92-A(4)
|
990--997
|
April 2009
|
| 119.pdf
|
Academic Journal
|
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
|
Impact of Well Edge Proximity Effect on Timing
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E91-A(12)
|
3461-3464
|
December 2008
|
| 111.pdf
|
Academic Journal
|
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
|
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3560-3568
|
December 2006
|
| 3.pdf
|
Academic Journal
|
T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, M. Hashimoto
|
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
|
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
| E89-A(12)
|
3666-3670
|
December 2006
|
| 5.pdf
|
Academic Journal
|
金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜
|
遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法
|
情報処理学会論文誌
| 44(5)
|
1301-1310
|
May 2003
|
| 21.pdf
|
International Conference
|
J. Chen, T. Kanamoto, H. Kando, M. Hashimoto
|
An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency
|
Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)
|
|
|
May 2018
|
| pdf
|
International Conference
|
Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye
|
Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process
|
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
|
|
397--400
|
November 2008
|
| 109.pdf
|
International Conference
|
T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto
|
Impact of Well Edge Proximity Effect on Timing
|
Proceedings of 37th European Solid-State Device Research Conference (ESSDERC)
|
|
115--118
|
September 2007
|
| 92.pdf
|
International Conference
|
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
|
Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design
|
Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)
|
|
227-230
|
May 2006
|
| 65.pdf
|
International Conference
|
T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto
|
Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction
|
Proceedings of International Workshop on Compact Modeling (IWCM)
|
|
51-56
|
January 2006
|
|
|
International Conference
|
T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, M. Hashimoto
|
Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters
|
Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)
|
|
149-155
|
January 2003
|
| 40.pdf
|
Domestic Conference
|
金本 俊幾, 阿久津滋聖, 中林 太美世, 一宮 敬弘, 蜂屋 孝太郎, 石川 博, 室本 栄, 小林 宏行, 橋本 昌宜, 黒川 敦
|
遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価
|
情報処理学会DAシンポジウム
|
|
265-270
|
July 2004
|
|
|
Domestic Conference
|
金本 俊幾, 佐藤 高史, 黒川 敦, 川上 善之, 岡 宏規, 北浦 智靖, 池内 敦彦, 小林 宏行, 橋本 昌宜
|
0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法
|
情報処理学会DAシンポジウム
|
|
149-154
|
July 2002
|
|
|
Domestic Conference
|
佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜
|
インダクタンスが配線遅延に及ぼす影響の定量的評価方法
|
第15回 回路とシステム(軽井沢)ワークショップ
|
|
493-498
|
April 2002
|
|
|
Workshop
|
T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, A. Ikeuchi, H. Kobayashi, M. Hashimoto
|
インダクタンスに起因する配線遅延変動の統計的予測手法
|
2002年電子情報通信学会ソサイエティ大会講演論文集
| (TA-2-4)
|
247-248
|
September 2002
|
|
|
