この検索内の頻出タグ: accelerator^:3 neural^:3 22nm^:2 accelerators^:2 cmos^:2 computing^:2 dbc^:2 edge-ai^:2 evaluation^:2 fsrms^:2 impact^:2 integrated^:2 jitter^:2 low-power^:2 network^:2 reliability^:2 soc^:2 system-on-chip^:2 ^:1 128.4^:1 13-34^:1 22^:1 292.2-to-321.4^:1 88.5^:1 8t^:1 access^:1 accurately^:1 ai^:1 allocation^:1 analysis^:1

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\title{\LARGE\bf 研究業績リスト}

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\section{論文誌}
\label{sec:0}

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\item
Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, ``A 292.2-To-321.4 Ghz Synchronized Source Generator with ‒58.7 Dbc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 Nm Cmos Technology,'' IEEE Transactions on Microwave Theory and Techniques,    採録済.
\item
M. Lou, J. Wang, H. Li, Z. Yang, Q. Cheng, J. Li, M. Hashimoto, and L. Lin, ``Area-Efficient and Low-Power {8T} {Compute-SRAM} Bitcell Design for Digital Compute-In-Memory Macros in 22nm {CMOS},'' IEEE Transactions on Circuits and Systems II,    採録済.
\item
W. Jin, Q. Cheng, Y. Liang, and M. Hashimoto, ``An 88.5 {fsrms} Integrated Jitter and ‒76.2 {dBc} Reference Spur {mmW} {PLL} Utilizing a Ripple Compensation Phase/Frequency Detector,'' IEEE Transactions on Circuits and Systems I: Regular Papers, volume 72, number 9, pages 4570-4583, September 2025.
\item
Q. Cheng, M. Huang, C. Man, A. Shen, L. Dai, H. Yu, and M. Hashimoto, ``Reliability Exploration of System-On-Chip with Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks,'' IEEE Transactions on Circuits and Systems I: Regular Papers, volume 70, number 10, 3978 -- 3991, October 2023.
\item
Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, ``A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier,'' IEEE Transactions on Circuits and Systems II, volume 70, number 6, 2246 - 2250, June 2023.
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\section{国際会議}
\label{sec:1}

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\item
Q. Cheng, H. Zhang, C.-H. Liang, M. Zhang, J.-J. Liou, J. Xiong, L. Lin, and M. Hashimoto, ``Tenpura: a General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-Fast Reliability Analysis,'' Proceedings of International Conference on Computer-Aided Design (ICCAD),    採録済.
\item
Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, ``A Scalable External Memory Access and On-Chip Storage Architecture for {Edge-AI} Accelerators --  Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --,'' Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED),   August 2025.
\item
Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, ``A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics,'' Digest of Symposium on VLSI Technology and Circuits,   June 2025.
\item
Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, ``A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing,'' Proceedings of IEEE Custom Integrated Circuits Conference (CICC),   April 2025.
\item
Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, ``{HachiFI:} a Lightweight {SoC} Architecture-Independent Fault-Injection Framework for {SEU} Impact Evaluation,'' Proceedings of Design, Automation and Test in Europe Conference (DATE),   March 2025.
\item
M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, ``{S3M:} Static Semi-Segmented Multipliers for Energy-Efficient {DNN} Inference Accelerators,'' Proceedings of IEEE International Conference on Computer Design (ICCD),  pages 16-23, October 2024.
\item
Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, ``A 13-34 {TOPS/W} {Edge-AI} Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping,'' Technical Digest of Asian Solid-State Circuits Conference (A-SSCC),   October 2024.
\item
Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, ``How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge {AI} {SoC} --,'' Proceedings of Design Automation Conference (DAC),   June 2024.
\end{enumerate}
以上．
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