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19 件の該当がありました． : このページのURL : HTML

論文誌

[1] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 Ghz Synchronized Source Generator with ‒58.7 Dbc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 Nm Cmos Technology," IEEE Transactions on Microwave Theory and Techniques, 採録済.

[2] Y. Li, M. Yoshida, Y. Gomi, Y. Deng, Y. Watanabe, S. Adachi, M. Itoh, G. Zhang, C. He, and M. Hashimoto, "Experimental Study of Proton-Induced Radiation Effects on DDR5 Modules," IEEE Transactions on Nuclear Science, volume 72, number 6, pages 1907-1918, June 2025. [pdf]

[3] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Vulnerability Estimation of DNN Model Parameters with Few Fault Injections," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E106-A, number 3, pages 523-531, March 2023. [pdf]

[4] G. L. Zhang, B. Li, X. Huang, X. Yin, C. Zhuo, M. Hashimoto, and U. Schlichtmann, "Virtualsync+: Timing Optimization with Virtual Synchronization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 41, number 12, pages 5526-5540, December 2022. [pdf]

[5] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow," IEEE Transactions on Nuclear Science, volume 68, number 8, pages 1668--1674, August 2021. [pdf]

国際会議

[1] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 採録済.

[2] Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), April 2025. [pdf]

[3] Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, "HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation," Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2025. [pdf]

[4] M. Zhang and M. Hashimoto, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," International collaboration Symposium on Information, Production and Systems (ISIPS), November 2024.

[5] M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, "S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 16-23, October 2024. [pdf]

[6] M. Hashimoto, Y. Zhang, and K. Ito, "Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards," Proceedings of International Conference on Solid State Devices and Materials (SSDM), September 2022.

[7] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections," Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 60-63, March 2022. [pdf]

[8] Y. Zhang, K. Ito, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.

[9] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.

[10] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018. [pdf]

[11] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009. [115.pdf]

[12] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008. [123.pdf]

[13] L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, "High Performance Current-Mode Differential Logic," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 720--725, January 2008. [98.pdf]

国内会議(査読付き)

[1] Zhang Mingtao, Cheng Quan, 粟野 皓光, Lin Longyang, 橋本 昌宜, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," 情報処理学会DAシンポジウム, 2024年.