List of works
この検索内の頻出タグ: accelerator:3 computing:2 edge-ai:2 neural:2 on-chip:2 system-on-chip:2 13-34:1 22nm:1 accelerators:1 access:1 allocation:1 analysis:1 architecture:1 bank:1 booth:1 booth-value-confined:1 capacitance:1 cmos:1 contiguity-aware:1 convolutional:1 data:1 deep:1 delay:1 effect:1 exploration:1 expressions:1 external:1 featuring:1 hyper-heterogeneous:1 in-orbit:1
- 論文誌
- [1] Q. Cheng, M. Huang, C. Man, A. Shen, L. Dai, H. Yu, and M. Hashimoto, "Reliability Exploration of System-On-Chip with Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, volume 70, number 10, 3978 -- 3991, October 2023. [pdf]
- [2] Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, "A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier," IEEE Transactions on Circuits and Systems II, volume 70, number 6, 2246 - 2250, June 2023. [pdf]
- [3] G. L. Zhang, B. Li, X. Huang, X. Yin, C. Zhuo, M. Hashimoto, and U. Schlichtmann, "Virtualsync+: Timing Optimization with Virtual Synchronization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 41, number 12, pages 5526-5540, December 2022. [pdf]
- [4] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]
- [5] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]
- 国際会議
- [1] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2025. [pdf]
- [2] Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), April 2025. [pdf]
- [3] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), October 2024. [pdf]