この検索内の頻出タグ: fault^:5 irradiation^:3 neutron^:3 test^:3 analyzing^:2 control^:2 dnn^:2 due^:2 errors^:2 flow^:2 gpus^:2 injection^:2 injections^:2 model^:2 parameters^:2 vulnerability^:2 128.4^:1 22^:1 22nm^:1 292.2-to-321.4^:1 accelerators^:1 access^:1 all^:1 allocation^:1 analysis^:1 architecture^:1 bank^:1 bits^:1 cards^:1 cmos^:1

12 件の該当がありました． : このページのURL : HTML

論文誌

[1] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 Ghz Synchronized Source Generator with ‒58.7 Dbc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 Nm Cmos Technology," IEEE Transactions on Microwave Theory and Techniques, 採録済.

[2] Y. Li, M. Yoshida, Y. Gomi, Y. Deng, Y. Watanabe, S. Adachi, M. Itoh, G. Zhang, C. He, and M. Hashimoto, "Experimental Study of Proton-Induced Radiation Effects on DDR5 Modules," IEEE Transactions on Nuclear Science, volume 72, number 6, pages 1907-1918, June 2025. [pdf]

[3] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Vulnerability Estimation of DNN Model Parameters with Few Fault Injections," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E106-A, number 3, pages 523-531, March 2023. [pdf]

[4] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow," IEEE Transactions on Nuclear Science, volume 68, number 8, pages 1668--1674, August 2021. [pdf]

国際会議

[1] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 採録済.

[2] Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), April 2025. [pdf]

[3] M. Hashimoto, Y. Zhang, and K. Ito, "Neutron-Induced Stuck Error Bits and Their Recovery in DRAMs on GPU Cards," Proceedings of International Conference on Solid State Devices and Materials (SSDM), September 2022.

[4] Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections," Proceedings of Design, Automation and Test in Europe Conference (DATE), pages 60-63, March 2022. [pdf]

[5] Y. Zhang, K. Ito, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.

[6] K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, "Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), October 2020.

[7] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009. [115.pdf]

[8] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008. [123.pdf]