
- 論文誌
- [1] M. Lou, J. Wang, H. Li, Z. Yang, Q. Cheng, J. Li, M. Hashimoto, and L. Lin, "Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS," IEEE Transactions on Circuits and Systems II, volume 72, number 11, pages 1605-1609, November 2025.
- [2] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 GHz Synchronized Source Generator with ‒58.7 dBc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 nm CMOS Technology," IEEE Transactions on Microwave Theory and Techniques, volume 73, number 10, pages 7572-7587, October 2025. [pdf]
- 国際会議
- [1] Q. Cheng, Z. Yang, H. Li, Q. Li, Z. Kong, G. Niu, Y. Liang, J. Li, J. Yoo, M. Hashimoto, and L. Lin, "A Radiation-Hardened Self-Healing Cmos Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), 採録済.
- [2] Q. Cheng, H. Zhang, C.-H. Liang, M. Zhang, J.-J. Liou, J. Xiong, L. Lin, and M. Hashimoto, "Tenpura: a General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-Fast Reliability Analysis," Proceedings of International Conference on Computer-Aided Design (ICCAD), October 2025. [pdf]
- [3] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2025. [pdf]
- [4] Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics," Digest of Symposium on VLSI Technology and Circuits, June 2025. [pdf]
- [5] Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), April 2025. [pdf]
- [6] Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, "HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation," Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2025. [pdf]
- [7] M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, "S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 16-23, October 2024. [pdf]
- [8] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), October 2024. [pdf]
- [9] Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, "How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --," Proceedings of Design Automation Conference (DAC), June 2024. [pdf]
- [10] K.-W. Lin, M. Hashimoto, and Y.-L. Li, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles Considering Traffic Uncertainties," Proceedings of International Symposium on Quality Electronic Design (ISQED), March 2018. [pdf]
- [11] K.-W. Lin, Y.-L. Li, and M. Hashimoto, "Near-Future Traffic Evaluation Based Navigation for Automated Driving Vehicles," Proceedings of IEEE Intelligent Vehicles Symposium (IV), pages 1465--1470, June 2017. [pdf]