この検索内の頻出タグ: 13-34^:1 accelerator^:1 analysis^:1 booth-value-confined^:1 capacitance^:1 cmos^:1 computing^:1 contiguity-aware^:1 delay^:1 edge-ai^:1 effect^:1 expressions^:1 featuring^:1 interconnect^:1 inverter^:1 mapping^:1 modeling^:1 nanometer^:1 near-memory^:1 on-chip^:1 overshooting^:1 polynomial^:1 processor^:1 second-order^:1 technologies^:1 tops/w^:1

3 件の該当がありました． : このページのURL : HTML

論文誌

[1] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, "Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 29, number 2, pages 250--260, February 2010. [134.pdf]

[2] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]

国際会議

[1] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), 採録済.