この検索内の頻出タグ: accelerators^:2 optimization^:2 timing^{:2 :1} 128.4^:1 22^:1 22nm^:1 292.2-to-321.4^:1 access^:1 allocation^:1 architecture^:1 architecture-independent^:1 bank^:1 cmos^:1 combinational^:1 components^:1 computing^:1 data^:1 dbc^:1 delay^:1 dnn^:1 edge-ai^:1 energy-efficient^:1 evaluation^:1 external^:1 fault-injection^:1 framework^:1 fsrms^:1 generator^:1 ghz^:1

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論文誌

[1] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 Ghz Synchronized Source Generator with ‒58.7 Dbc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 Nm Cmos Technology," IEEE Transactions on Microwave Theory and Techniques, 採録済.

[2] G. L. Zhang, B. Li, X. Huang, X. Yin, C. Zhuo, M. Hashimoto, and U. Schlichtmann, "Virtualsync+: Timing Optimization with Virtual Synchronization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, volume 41, number 12, pages 5526-5540, December 2022. [pdf]

国際会議

[1] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 採録済.

[2] Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), April 2025. [pdf]

[3] Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, "HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation," Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2025. [pdf]

[4] M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, "S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 16-23, October 2024. [pdf]

[5] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018. [pdf]

[6] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009. [115.pdf]

[7] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008. [123.pdf]

[8] L. Zhang, J. Liu, H. Zhu, C-K Cheng, and M. Hashimoto, "High Performance Current-Mode Differential Logic," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 720--725, January 2008. [98.pdf]