Frequent tags in this search: design^:5 voltage^:5 activation-aware^:4 assignment^:4 mode-wise^:4 scaling^:4 slack^:4 bit-width^:3 critical^:3 energy^:3 isolation^:3 minimization^:3 over-scalable^:3 path^:3 voltage-scalable^:2 adaptation^:1 are^:1 asa^:1 circuit^:1 comparing^:1 compatible^:1 high-end^:1 highly^:1 in-situ^:1 isp^:1 low-power^:1 methodology^:1 monitors^:1 performance^:1 power^:1

8 publications are found. : URL for this page. : HTML

@article{id575,
         title = {Activation-aware Slack Assignment Based Mode-wise Voltage Scaling for Energy Minimization},
        author = {T. Cheng and Y. Masuda and J. Nagayama and Y. Momiyama and J. Chen and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E105-A},
        number = {3},
         pages = {497--508},
         month = {3},
          year = {2022},
}

@article{id576,
         title = {Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling},
        author = {Y. Masuda and  J. Nagayama and  T. Cheng and  T. Ishihara and  Y. Momiyama and  and M. Hashimoto},
       journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {105-A},
        number = {3},
         pages = {509--517},
         month = {3},
          year = {2022},
}

@article{id560,
         title = {Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design},
        author = {Y. Masuda and J. Nagayama and T. Cheng and T. Ishihara and Y. Momiyama and M. Hashimoto},
       journal = {Proceedings of Design, Automation and Test in Europe Conference (DATE)},
         month = {2},
          year = {2021},
}

@article{id559,
         title = {Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization},
        author = {T. Cheng and Y. Masuda and J. Nagayama and Y. Momiyama and J. Chen and M. Hashimoto},
       journal = {Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)},
         pages = {284 -- 290},
         month = {1},
          year = {2021},
}

@article{id550,
         title = {Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling},
        author = {Y. Masuda and J. Nagayama and T. Cheng and T. Ishihara and Y. Momiyama and M. Hashimoto},
       journal = {International Workshop on Logic and Synthesis (IWLS)},
         month = {7},
          year = {2020},
}

@article{id510,
         title = {Activation-aware Slack Assignment {(ASA)} for Mode-wise Power Saving in High-End {ISP}},
        author = {J. Nagayama and Y. Masuda and M. Takeshige and Y. Ogawa and M. Hashimoto and Y. Momiyama},
       journal = {Design Automation Conference, Designer/IP Track},
         month = {6},
          year = {2019},
}

@article{id486,
         title = {Comparing Voltage Adaptation Performance between Replica and In-Situ Timing Monitors},
        author = {Y. Masuda and J. Nagayama and H. Takeno and Y. Ogawa and Y. Momiyama and M. Hashimoto},
       journal = {Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)},
         month = {11},
          year = {2018},
}

@article{id570,
         title = {Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization},
        author = {T.-Y. Cheng and  Y. Masuda and  J. Nagayama and  Y. Momiyama and  J. Chen and  M. Hashimoto},
       journal = {電子情報通信学会 VLSI設計技術研究会},
         month = {3},
          year = {2021},
}