この検索内の頻出タグ: 13-34^:1 22nm^:1 8t^:1 accelerator^:1 area-efficient^:1 bitcell^:1 booth-value-confined^:1 capacitance^:1 cmos^:1 compute-in-memory^:1 compute-sram^:1 computing^:1 contiguity-aware^:1 design^:1 digital^:1 edge-ai^:1 expressions^:1 featuring^:1 imager^:1 interconnect^:1 low-power^:1 macros^:1 mapping^:1 near-memory^:1 network^:1 neural^:1 neuromorphic^:1 on-chip^:1 pixels^:1 polynomial^:1

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論文誌

[1] M. Lou, J. Wang, H. Li, Z. Yang, Q. Cheng, J. Li, M. Hashimoto, and L. Lin, "Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS," IEEE Transactions on Circuits and Systems II, 採録済.

[2] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005. [10.pdf]

国際会議

[1] Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics," Digest of Symposium on VLSI Technology and Circuits, 採録済.

[2] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), October 2024. [pdf]