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論文誌

[1] M. Lou, J. Wang, H. Li, Z. Yang, Q. Cheng, J. Li, M. Hashimoto, and L. Lin, "Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS," IEEE Transactions on Circuits and Systems II, 採録済.

国際会議

[1] Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics," Digest of Symposium on VLSI Technology and Circuits, 採録済.

[2] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 採録済.

[3] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), October 2024. [pdf]