List of works
この検索内の頻出タグ: cmos:2 dbc:2 fsrms:2 imager:2 integrated:2 jitter:2 radiation-hardened:2 self-healing:2 space:2 128.4:1 22:1 292.2-to-321.4:1 88.5:1 accelerators:1 access:1 allocation:1 annealing:1 applications:1 architecture:1 bank:1 compensation:1 compression:1 data:1 detector:1 edge-ai:1 external:1 generator:1 ghz:1 layer-wise:1 memory:1
- 論文誌
- [1] Y. Liang, S. Chen, H. Zhang, L. Lin, Q. Cheng, and M. Hashimoto, "A 292.2-To-321.4 GHz Synchronized Source Generator with ‒58.7 dBc Spurious Tone and 128.4 Fsrms Integrated Jitter in 22 nm CMOS Technology," IEEE Transactions on Microwave Theory and Techniques, volume 73, number 10, pages 7572-7587, October 2025. [pdf]
- [2] W. Jin, Q. Cheng, Y. Liang, and M. Hashimoto, "An 88.5 fsrms Integrated Jitter and ‒76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector," IEEE Transactions on Circuits and Systems I: Regular Papers, volume 72, number 9, pages 4570-4583, September 2025. [pdf]
- 国際会議
- [1] Q. Cheng, Z. Yang, H. Li, Q. Li, Z. Kong, G. Niu, Y. Liang, J. Li, J. Yoo, M. Hashimoto, and L. Lin, "A Radiation-Hardened Self-Healing Cmos Imager with Online Pixel/Logic Annealing and Tile-Adaptive Compression for Space Applications," Technical Digest of International Solid-State Circuits Conference (ISSCC), 採録済.
- [2] Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, "A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators -- Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation --," Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2025. [pdf]
- [3] Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics," Digest of Symposium on VLSI Technology and Circuits, June 2025. [pdf]